Making RAM at Home [video]

TL;DR: In a Class-100 cleanroom built in his backyard, the author fabricated the first-ever working 5×4 DRAM array using homemade semiconductor gear, with sub-micron gate length, 12.3 fF capacitors, 200 ns write time, and a 2 ms refresh requirement. ## Prices Are Insane—So I Built My Own Memory prices have gone berserk. AI demand has dragged GPUs, phones, and PCs into the same feeding frenzy, while Micron, Samsung, and SK hynix keep the industry on a short leash. A new fab costs tens of billions and takes years to ramp. Instead of waiting, I turned a backyard shed into a Class-100 cleanroom and built every tool from scratch—goal: make RAM at home. ## DRAM 101 Zoom in on a memory chip and you see a grid. Each intersection is one transistor plus one storage capacitor. - Transistor = switch - Capacitor = tiny battery Turn the switch on to charge = write a 1; off to hold the charge. Reading flips the switch again—charge flows out and is sensed—but the act destroys the data, so the cell must be refreshed periodically. ## Layout: 5×4 Test Array I drew a 5×4 tile that can later be tiled out like quiltwork. Each cell is still one transistor, one capacitor, with a sub-micron gate length target. The colored layers are a floor plan; the chip is built one storey at a time. ## Starting Silicon: Cleave, Clean, Oxidize 1. Score a wafer with a diamond scribe along the crystal plane—silicon snaps like chocolate into die. 2. Acetone + IPA ultrasonic bath to strip particles and organics. 3. 1 100 °C dry-O₂ furnace grows 3 300 Å of oxide—lime-green glass that will serve as a later mask. ## First Litho: Open Windows Glass won’t hold photoresist, so spin LOR adhesion promoter, bake 5 min @ 170 °C; then spin resist, bake 2 min @ 100 °C for ~1 µm thickness. - Mask aligner + UV: exposed areas generate photoacid. - Mild-alkali developer: acid–base salt washes away, opening resist. Mask #1 defines “windows”. A microscope stepper shrinks the image onto the die; high-NA objective hits sub-micron. After develop, dry etch bores through the oxide to bare silicon; hot DMSO strips the resist. ## Source/Drain: Phosphorus Spin-On Glass Industrial ion implanters cost millions and a room. Borrowing from ProjectsInFlight, I mix homemade phosphorus-doped spin-on glass. - Test chip: high resistance before doping, sheet resistance plummets after drive-in—degenerate doping achieved. Main wafer: spin P-glass → ramp bake to drive off solvent → 1 100 °C 5 min drive → HF strip glass → 1 000 °C 10 min second drive, yielding shallow S/D junctions. ## Gate Oxide & Capacitor Dielectric LOR + resist again, mask #2 aligns between source and drain to open “channel + capacitor” zone. After develop, HF removes the thick oxide there—gate and capacitor oxides need their own, thinner recipe. Channel clean in piranha (H₂SO₄/H₂O₂), then 950 °C 38 min to grow 200 Å (20 nm) of fresh oxide—serving as both gate dielectric and capacitor dielectric. Cross-section: thick oxide ring remains; center is 20 nm thin-oxide. ## Contacts & Metal Lines The whole surface is now re-oxidized; we need vias to wire things up. - LOR + resist → contact mask → HF opens holes to silicon. Final metal layer: - LOR + resist → top-level mask exposure. - Table-top sputter gun Ar⁺-bombs an Al target, metal atoms “spray-paint” the surface. - Hot DMSO lift-off: resist dissolves and carries off unwanted Al, leaving patterned traces—nanoscale screen-printing complete. ## Microscope Checkout Die cross-section matches the cartoon 1:1: transistor, capacitor, wires—one DRAM cell, born in a garage. ## Living-Room Electrical Test A micromanipulated probe station with picometer-sharp needles lands on bond pads, wired to a semiconductor parameter analyzer. **Transistor curves:** Each trace is a different gate voltage; device turns off at low V_G and on at high V_G like a dimmer. S/D spacing <1 µm; high voltages show short-channel punch-through—classic scaling headache. **Capacitor:** CV sweep peaks at 12.3 fF, within spitting distance of the few-fF design target. **1-bit DRAM cell:** Transistor charges the capacitor to 3 V in 200 ns; leakage kills the data in ~2 ms, so refresh is required—commercial spec is 64 ms, we’ve got work to do. ## Historic First: Home-Made RAM The 5×4 array reads and writes successfully. It stores only a handful of bits and won’t run Doom, but it’s the first working RAM ever built at home. Next up: tile out a bigger array and hook it to a computer—stay tuned. Source: https://www.youtube.com/watch?v=h6GWikWlAQA