EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

# EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models
Source: [https://arxiv.org/html/2607.13416](https://arxiv.org/html/2607.13416)
Guanglei Zhou1, Chen\-Chia Chang1, Yikang Shen2, Jonathan Ku1, Isaac Jacobson1, Jingyu Pan1, Yiran Chen1, Xin Zhang31Electrical and Computer Engineering, Duke University, Durham, USA2MIT\-IBM Watson AI Lab, Cambridge, USA3IBM T\. J\. Watson Research Center, Yorktown Heights, USA1\{guanglei\.zhou, chenchia\.chang, jonathan\.ku, isaac\.jacobson, jingyu\.pan, yiran\.chen\}@duke\.edu2yikang\.shen@ibm\.com3xzhang@us\.ibm\.com

###### Abstract\.

Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands\. Recent advances have applied sequence\-to\-sequence fine\-tuning on pretrained language models to directly generate circuit topologies from user specifications in a single pass\. However, these one\-shot generation methods failed to generate complex circuits due to their exponentially growing search spaces and limited training datasets\. In this paper, we presentEXPLORE, a search\-enhanced framework that integrates simulator\-guided Monte Carlo Tree Search \(MCTS\) with transformer\-based decoding to enable test\-time scaling for analog topology generation\. By leveraging language\-model priors and bypassing high\-confidence structural tokens, EXPLORE allocates expensive simulator budget primarily toward topology\-altering decisions during search\. On a 6\-component benchmark at a tight tolerance of 0\.01, EXPLORE raises the success rate from 12% for one\-shot generation and 33% for a sampling\-and\-filter baseline to 65%, and lowers MSE by over 20× relative to sampling\-and\-filter under the same search budget\. These results establish EXPLORE as the first framework to integrate structured test\-time search with LM decoding for analog topology generation, and a practical step toward scaling LLM\-driven design automation\.

††copyright:none††conference:; ;## 1\.Introduction

![Refer to caption](https://arxiv.org/html/2607.13416v1/x1.png)Figure 1\.Topology space grows combinatorially with circuit complexity, while collected topologies remain limited, resulting in increasingly sparse design\-space coverage\(Fanet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib7); Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)\.Analog circuit topology design sits at the heart of modern electronic systems, enabling everything from efficient power conversion to high\-speed signal processing\. As device requirements proliferate, varying voltage\-conversion ratios, efficiency targets, and performance specifications, the burden on designers to craft bespoke topologies grows heavier\. Traditional workflows remain largely manual, demanding extensive domain expertise and hundreds of simulation iterations per new requirement, which in turn prolongs development cycles and delays time\-to\-market\. To meet these challenges, automating the topology design process has become essential: by embedding search and learning methods directly into the design flow, engineers can rapidly explore vast design spaces, reduce iteration counts, and accelerate the creation of optimized analog circuits\.

Early works\(Fanet al\.,[2021](https://arxiv.org/html/2607.13416#bib.bib5); Zhao and Zhang,[2022](https://arxiv.org/html/2607.13416#bib.bib8); Luet al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib6)\)leverage reinforcement learning \(RL\) or Bayesian optimization to discover valid topologies using simulation feedback\. These methods reduce evaluation costs and produce functional designs, but suffer from two key limitations: \(1\) they must restart search or retrain policies for every new specification, and \(2\) they have only demonstrated success on small, relaxed 3–5 component circuits\. Without access to prior knowledge across tasks, such methods remain inefficient and unscalable for practical usage\.

LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)reframed topology generation as a sequence\-to\-sequence problem for autoregressive language models, introducing several text\-based circuit formulations\. Trained on a corpus of 132k 3—5 component converter topologies, LaMAGIC achieved strong results within this regime\. However, as Figure[1](https://arxiv.org/html/2607.13416#S1.F1)illustrates, the topology search space grows exponentially with component count\. At six components, a good dataset coverage becomes impractical: with an average simulation time of 9 seconds per topology, enumerating the full design space would require over 2000 CPU\-days\. Consequently, LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)struggles to transfer knowledge from 345 components to six, and scaling further to complex circuits with 8–10 components becomes infeasible\. This gap highlights a fundamental bottleneck: existing approaches, constrained by limited datasets, cannot scale topology generation on their own\. Overcoming this limitation requires not only new computing paradigms, such as search\-enhanced test\-time scaling techniques, but also novel dataset collection strategies that efficiently harvest high\-quality training data in larger, more complex circuit spaces\.

In this work, we proposeEXPLORE, a search\-enhanced language model framework for automated analog topology generation\. EXPLORE integrates simulator\-guided Monte Carlo Tree Search \(MCTS\) with transformer\-based decoding to leverage inference\-time compute for generating higher\-quality and more scalable analog circuit topologies\. Building on text\-based circuit formulations, our framework combines pretrained language\-model priors with simulator feedback to guide exploration toward valid and high\-performance circuit structures\. In addition, we construct a large\-scale dataset of higher\-complexity analog topologies to study the scalability of language\-model\-based topology generation beyond prior works\.

The main contributions of this work are as follows:

- •First test\-time\-scaling framework\.EXPLORE is the first work to bring test\-time scaling to analog topology generation, along two axes: an LM\-guided MCTS as a test\-time decoder, and the same search reused as a model\-native data\-collection engine\.
- •Structured\-token filtering\.We bypass structural tokens in the text\-based circuit formulation via p\-filtering \(p=0\.99p=0\.99\), skipping 24–48% of expansive simulation trials and making scaling to higher\-complexity circuits computationally feasible\.
- •Superior generation success and query efficiency\.At a tight tolerance of 0\.01 on 6\-comp, EXPLORE raises the success rate from 12% for one\-shot LaMAGIC and 33% for its sampling\-and\-filter variant to 65%, with over 20× lower MSE than sampling\-and\-filter under the same search budget and faster convergence than our MCTS\-Base ablation within 100 generations\.
- •Scalability beyond one\-shot generation method\.EXPLORE enables generation at 7, 8, and 9 components, a regime where one\-shot LM decoding collapses to near\-zero success and which prior 3–6 component datasets do not cover\.

## 2\.Preliminaries

### 2\.1\.Analog topology design

![Refer to caption](https://arxiv.org/html/2607.13416v1/x2.png)Figure 2\.\(a\) An example power converter circuit and \(b\) its corresponding graph representation\.In this work, we address the same problem as LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\): generating customized power converters that meet specific voltage conversion ratios and efficiency targets\. Thevoltage conversion ratiois the output\-to\-input voltage ratio, while power conversionefficiencyis the output\-to\-input power ratio\. Theduty cycle\(a number between 0\-1\) is a design parameter, which controls the ON time of switches, affecting performance\. We use five discrete duty cycles:0\.1,0\.3,0\.5,0\.7,0\.9\{0\.1,0\.3,0\.5,0\.7,0\.9\}\. We represent circuits as hypergraphsGGwith verticesVVand hyperedgesEE\. Vertices include three terminals \(inputVINV\_\{\\text\{IN\}\}, outputVOUTV\_\{\\text\{OUT\}\}, and ground GND\) and four component types \(capacitorsCC, inductorsLL, and switchesSaS\_\{a\},SbS\_\{b\}\)\. Hyperedges define connections between components and terminals\. Figure[2](https://arxiv.org/html/2607.13416#S2.F2)shows an example converter with its hypergraph representation\.

Problem Statement: Given verticesVV, target conversion ratiorr, and efficiencyη\\eta, our model generates connectionsEEand selects duty cyclessto create a circuit meeting both performance requirements\.

### 2\.2\.Search\- and optimization\-based methods

Classical analog topology generation treats the problem as a black\-box search over a combinatorial graph space guided by simulator feedback\.\(Fanet al\.,[2021](https://arxiv.org/html/2607.13416#bib.bib5)\)models power converter design as a sequential decision process using a UCT\-based RL tree with physics\-guided pruning, achieving up to 67% fewer SPICE calls than genetic or random search\.\(Zhao and Zhang,[2022](https://arxiv.org/html/2607.13416#bib.bib8)\)applies deep RL to op\-amp synthesis, combining symbolic analysis and memorization to converge to feasible designs within hours but requiring retraining for each circuit class\.\(Luet al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib6)\)pairs a variational autoencoder with Bayesian optimization to identify spec\-compliant topologies more efficiently than graph\-grammar engines, and\(Fanet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib7)\)accelerates the same search loop with a graph\-transformer SPICE surrogate\. More recently, ADO\-LLM\(Yinet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib22)\)replaces a hand\-tuned acquisition function with in\-context learning over an LLM to seed Bayesian optimization for analog sizing\. Across this line of work, each new specification still triggers a fresh search or policy retraining, and the demonstrated regime is small\.

### 2\.3\.Language model\-based methods

A recent paradigm shift reframes topology generation as a conditional sequence generation task: given a target specification, the model decodes a circuit description token\-by\-token\. AnalogCoder\(Laiet al\.,[2025](https://arxiv.org/html/2607.13416#bib.bib4)\), AnalogCoder\-Pro\(Laiet al\.,[2026](https://arxiv.org/html/2607.13416#bib.bib20)\), AnalogXpert\(Zhanget al\.,[2025](https://arxiv.org/html/2607.13416#bib.bib18)\), and Artisan\(Chenet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib9)\)prompt or fine\-tune general or domain LLMs to emit SPICE\-style code or operate over curated subcircuit libraries, primarily targeting general circuit*families*\. Closest to our setting, LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)fine\-tunes an encoder–decoder transformer to map a target\(v⋆,η⋆\)\(v^\{\\star\},\\eta^\{\\star\}\)to a converter topology in one autoregressive pass\. Subsequent works have optimized this paradigm by compressing adjacency representations toO​\(\|V\|\)O\(\|V\|\)\(Changet al\.,[2025](https://arxiv.org/html/2607.13416#bib.bib2),[2026](https://arxiv.org/html/2607.13416#bib.bib3)\), and applying RL fine\-tuning\(Vijayaraghavanet al\.,[2025](https://arxiv.org/html/2607.13416#bib.bib21)\)\. CktGNN\(Donget al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib15)\)pairs adjacency with a graph VAE, and AnalogGenie\(Gaoet al\.,[2025a](https://arxiv.org/html/2607.13416#bib.bib27)\)/AnalogGenie\-Lite\(Gaoet al\.,[2025b](https://arxiv.org/html/2607.13416#bib.bib19)\)adopt Eulerian\-circuit and device\-pin representations\. All of these remain*one\-shot*generators: they expend their entire model capacity on a single decoded sequence, with no mechanism for spending extra compute when the first attempt is structurally invalid or off\-spec\. For complex circuit creation that requires iterative refinement and simulator feedback, this one\-shot paradigm is highly inefficient\. Diverging from all prior work, EXPLORE introduces test\-time scaling through a structured search framework guided by simulator feedback\. EXPLORE keeps the text\-based formulation but reframes generation as a guided search, drawing on the search\-augmented LLM decoding literature\(Liet al\.,[2022](https://arxiv.org/html/2607.13416#bib.bib17); Haoet al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib25); Yaoet al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib26)\)to spend additional inference\-time compute with simulator feedback on tokens where the model is uncertain\.

### 2\.4\.Complex power converter datasets: prior corpora and challenges

The lack of sufficiently large analog circuit datasets continues to hinder the development of AI\-based generative methods for automating analog IC design\. Prior corpora such as AnalogGenie\(Gaoet al\.,[2025a](https://arxiv.org/html/2607.13416#bib.bib27)\), Align\(Kunalet al\.,[2019](https://arxiv.org/html/2607.13416#bib.bib14)\), CktGNN\(Donget al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib15)\), AMSNet\(Taoet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib16)\), AMSnet\-KG\(Shiet al\.,[2025](https://arxiv.org/html/2607.13416#bib.bib24)\), and AICircuit\(Mehradfaret al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib23)\)prioritize breadth, covering diverse circuit families with only thousands of examples per circuit type\. Despite the substantial manual effort required to curate these samples from textbooks and datasheets, the per\-type sample sizes remain too small for a model to learn the internal dynamics of complex circuits\. In contrast, we prioritize on power converters and explore scaling towards higher\-component topologies within a single circuit class\.

Scaling a power converter dataset to higher component counts, however, introduces three compounding challenges: \(1\) the learning task becomes more complex, so substantially more training samples are required; \(2\) the fraction of invalid or useless topologies \(e\.g\., disconnected graphs or near\-zero\-efficiency circuits\) rises sharply; and \(3\) the probability that a purely random arrangement yields an efficient converter shrinks rapidly as the search space grows combinatorially\. These obstacles motivate the two\-stage construction pipeline detailed in Section[3\.2](https://arxiv.org/html/2607.13416#S3.SS2)\.

## 3\.Search\-enhanced language model framework

![Refer to caption](https://arxiv.org/html/2607.13416v1/x3.png)Figure 3\.\(a\) A circuit example of float\-input adjacency\-based matrix formulation for the edge generation task, highlighting its inefficiency due to structural tokens\. \(b\) Illustration of the EXPLORE framework pipeline through a step\-by\-step example of leveraging an MCTS algorithm to guide the Transformer generation for analog circuit topology\.We build on LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\), whose text\-based formulations for circuit generation include the float\-input adjacency\-matrix formulation \(FM\), which achieved the best MSE on 6\-component circuits\. As shown in Figure[3](https://arxiv.org/html/2607.13416#S3.F3)\(a\), FM represents circuit connections as an adjacency matrix over a hypergraph, with distinct tokens <no edge\>, <edge 1\>, <edge 2\>, and <both edges\> indicating the connection type between each vertex pair\. A property we exploit below is that more than half of the tokens in an FM sequence are*structural*: they keep the formulation syntactically legal but carry no topological choice \(highlighted in Figure[3](https://arxiv.org/html/2607.13416#S3.F3)\(a\)\), which is the opening that p\-filtering exploits\.

Although our pipeline follows the PUCT\-style LM\-guided MCTS template used for code generation\(Liet al\.,[2022](https://arxiv.org/html/2607.13416#bib.bib17); Zhanget al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib28)\), three properties of analog topology generation reshape almost every design choice\. \(i\)*The search target is a graph, not text\.*A circuit topology is an undirected \(hyper\)graph; the FM token stream is just one serialization of its adjacency matrix, so the actual decision space lives over edges between component pairs rather than over the surface tokens that the LM emits\. \(ii\)*Not all tokens are decisions\.*As noted above, structural tokens of FM carry no topological choice; in code generation, by contrast, nearly every token changes program semantics\. Spending simulator budget on forced tokens is pure waste, which makes p\-filtering structurally well\-motivated rather than a generic engineering speedup\. \(iii\)*Each evaluation is orders of magnitude more expensive\.*A single NGSPICE simulation costs roughly 4 seconds to a few minutes, versus milliseconds for a typical unit test in code\-generation settings\. Simulator budget, not search depth, is the dominant constraint: LM priors focus expansion on plausible edges, p\-filtering removes forced moves, and we beam\-complete partial topologies before simulating so every simulator call has a chance of returning useful reward\.

As illustrated in Figure[3](https://arxiv.org/html/2607.13416#S3.F3)\(b\), EXPLORE addresses these constraints with a single MCTS loop guided by transformer LM priors\. Each iteration selects a node with PUCT, expands either by auto\-committing a high\-confidence \(forced\) token via p\-filtering or by spawning top\-kkchildren at a genuine decision point, evaluates by beam\-completing the partial topology and simulating it in NGSPICE, and backpropagates the resulting reward\. The following subsections detail each step\.

### 3\.1\.LM\-guided topology search

Algorithm[1](https://arxiv.org/html/2607.13416#alg1)summarizes the procedure; we detail each phase below\.

Selection\.We apply PUCT\-style action priors \(in the spirit of AlphaCode\(Liet al\.,[2022](https://arxiv.org/html/2607.13416#bib.bib17)\)and PG\-TD\(Zhanget al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib28)\)\) to LM\-guided MCTS over circuit tokens: the language\-model probability of the child action token enters the UCB exploration term as the action priorP​\(a∣s\)P\(a\\mid s\), biasing selection toward likely and under\-explored continuations\. A tunable exploration constantcccontrols the trade\-off, with higherccencouraging broader search\.

Expansion\.After selecting a node, we first applyp\-filtering: if the language model assigns probability≥p\\geq pto its top\-1 token \(we usep=0\.99p\{=\}0\.99\), we auto\-commit that token and append it to the current node without spawning new children\. This pattern is empirically dominated by structural tokens of the FM representation that carry no topological choice\. Note that p\-filtering is the*opposite*of top\-pp\(nucleus\) sampling: nucleus sampling*prunes low\-probability*tokens to limit diversity, whereas p\-filtering*skips high\-probability*tokens that the model is already certain about, so as not to spend simulator budget on forced moves\. When no token exceeds the threshold, we applytop\-kksamplingto generate multiple child nodes, each representing an extended partial topology\.

Evaluation\.Since partial topologies cannot be directly simulated, we use beam search to complete the sequence from the current node, using a predefined prefix and beam widthbb\. The completed topology is then evaluated with NGSPICE to obtain circuit\-level performance metrics \(output voltagevvand conversion efficiencyee\), which are compared to the target\(v∗,e∗\)\(v^\{\*\},e^\{\*\}\)using the reward

\(1\)r=0\.5⋅max⁡\(0,1−\|v−v∗\|\)\+0\.5⋅max⁡\(0,1−\|e−e∗\|\),r\\;=\\;0\.5\\cdot\\max\\\!\\big\(0,\\,1\-\|v\-v^\{\*\}\|\\big\)\\;\+\\;0\.5\\cdot\\max\\\!\\big\(0,\\,1\-\|e\-e^\{\*\}\|\\big\),clipped to\[0,1\]\[0,1\]\. The0\.5/0\.50\.5\{/\}0\.5weighting is an unweighted average of voltage and efficiency error; tuning this weighting is left to future work\.

Backpropagationuses the standard PUCT\-style mean backup: each ancestor accumulates the leaf reward and exposesn​o​d​e\.v​a​l​u​e=1N​∑irinode\.value=\\tfrac\{1\}\{N\}\\sum\_\{i\}r\_\{i\}, the running average over theNNrollouts that pass through it\.

Algorithm 1MCTS\-based token generation1:root: initial state;

cc: UCB exploration parameter;

2:

kk: max children per node;

bb: beam search width;

3:

pp: threshold for structural token filtering

4:Best sequence from MCTS

5:Initialize tree with root node

6:for

i=1i=1to

m​a​x​\_​r​o​l​l​o​u​t​smax\\\_rolloutsdo

7:

n​o​d​e←r​o​o​tnode\\leftarrow root⊳\\trianglerightSelection

8:while

n​o​d​enodehas childrendo

9:

n​o​d​e←node\\leftarrowSelect child using UCB

10:whilelen\(node\.top\-p tokens\)==1do⊳\\trianglerightp\-filtering

11:

n​o​d​e←node\\leftarrowCONCAT\(node,

n​e​x​t​\_​t​o​k​e​n​snext\\\_tokens\)

12:

n​e​x​t​\_​t​o​k​e​n​s←next\\\_tokens\\leftarrowtop\-

kktokens⊳\\trianglerightExpansion

13:for

t​o​k​e​n∈n​e​x​t​\_​t​o​k​e​n​stoken\\in next\\\_tokensdo

14:Add new child node for

t​o​k​e​ntokento tree

15:

s​e​q​u​e​n​c​e←sequence\\leftarrowPerform beam search⊳\\trianglerightEvaluation

16:

r←r\\leftarrowObtain reward via simulation

17:Backpropagate\(node,

rr\)⊳\\trianglerightBackpropagation

18:returnsequence with the highest reward

### 3\.2\.Two\-stage dataset construction

To overcome the three scaling challenges identified in Section[2\.4](https://arxiv.org/html/2607.13416#S2.SS4), we construct our power\-converter corpus in two stages: we first expand the random\-enumeration pipeline to bootstrap higher\-component data, then close the loop by using the trained model itself, guided by the search procedure above, as a high\-quality data generator\.

Stage 1: expanding the random\-enumeration pipeline\.We extend the random topology generator of LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)beyond the 3–5 component regime to 6–10 components\. We predefine a pool of candidate components \(capacitors and inductors at various values, and the two switch types\), sample the target number of components, add the three terminalsVINV\_\{\\text\{IN\}\},VOUTV\_\{\\text\{OUT\}\}, and GND, and draw a random connected topology; each candidate is then simulated in NGSPICE and only valid circuits are retained\. Randomizing both the component selection and the connectivity yields topological diversity, but the yield of this pipeline degrades with scale exactly as challenges \(2\) and \(3\) predict: for the 7\-component set we generated 300,000 circuits and only 255,707 \(85\.2%\) were structurally valid, and the vast majority of those exhibit low efficiency\. This makes random enumeration alone impractical for building large high\-quality datasets at higher component counts\.

Stage 2: model\-native data collection\.Once a model has acquired a basic understanding of the formulation from Stage\-1 data, we reuse the trained model together with the EXPLORE framework as a data generator\. Because the LM prior biases expansion toward plausible edges and simulator feedback steers the search toward high\-efficiency targets, model\-native collection attains a far higher useful\-sample yield than random enumeration: on 6\-component circuits it cuts the fraction of sub\-2%\-efficiency topologies from 66\.1% to 18\.2% and raises the fraction above 90% efficiency from 8\.3% to 23\.3% \(analyzed in detail in Appendix[B\.3](https://arxiv.org/html/2607.13416#A2.SS3)\)\. Using this pipeline we assemble, to our knowledge, the largest 6\-component converter dataset to date \(350k samples\), substantially exceeding the 120k 3–5 component public release of LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)\.

Table 1\.Performance on the 6\-comp at thresholdt=0\.01t=0\.01for both 1 k and 32 k training\-data budgets\. All methods use up to 100 Transformer generations\.![Refer to caption](https://arxiv.org/html/2607.13416v1/x4.png)

\\phantomsubcaption

\\phantomsubcaption

\\phantomsubcaption

\(a\)Runtime illustration\.

Figure 4\.Comparison of success rates and runtime analysis on the 6\-comp benchmark \(FM\-1k\)\.\([4](https://arxiv.org/html/2607.13416#S3.F4)\): final success rate under varying error tolerances\. \([4](https://arxiv.org/html/2607.13416#S3.F4)\): success rate over iterations att=0\.01t\{=\}0\.01under different exploration constantsc∈\{0\.5,1,4\}c\\in\\\{0\.5,1,4\\\}\. \([4](https://arxiv.org/html/2607.13416#S3.F4)\): success rate over iterations att=0\.01t\{=\}0\.01under differentpp\-filtering thresholdsp∈\{0\.5,0\.7,0\.9,0\.99\}p\\in\\\{0\.5,0\.7,0\.9,0\.99\\\}at fixedc=4c=4\. \([4\(a\)](https://arxiv.org/html/2607.13416#S3.F4.sf1)\) Runtime breakdown and total evaluation time for EXPLORE\.

## 4\.Experimental results

### 4\.1\.Experiment setup

Baseline algorithms\.We compare EXPLORE with four decoding baselines\.Greedyis the one\-shot generation used in LaMAGIC\.Beam Searchuses Transformer beam search \(beam size 20\) without simulator feedback\.Sampling and filtering \(S\+F\)samples a set of topologies \(temperature 1\.2, top\-kkwithk=3k\{=\}3to avoid invalid tokens\), simulates each to measurevoutv\_\{\\text\{out\}\}and efficiency, and returns the candidate closest to the target; this mirrors AlphaCode\(Liet al\.,[2022](https://arxiv.org/html/2607.13416#bib.bib17)\)and a baseline in PG\-TD\(Zhanget al\.,[2023](https://arxiv.org/html/2607.13416#bib.bib28)\)\.MCTS\-Baseis our MCTS variant that uses UCB for node selection but ignores LLM token probabilities, treating all equal\-count children uniformly, thereby isolating the benefit of LLM\-guided priors\.

Models and datasets\.Large amount of data for circuits with a higher number of components can be difficult to obtain\. To reuse existing knowledge, similar to the LaMAGIC’s setting, we extend models trained with 3,4,5\-components to be finetuned with 1k and 32k 6\-component circuits and leverage our decoding algorithm to evaluate\. We follow LaMAGIC\(Changet al\.,[2024](https://arxiv.org/html/2607.13416#bib.bib1)\)to use an encoder\-decoder transformer structure with Flan\-T5\-base pretrained weights\. We add a shared linear layer to replace the word embedding layer for numeric inputs\. We train the model via conditional generation to learn the mapping between input\-output pairs\. Model trained withnnsamples using FM formulation is denoted as FM\-nn\. As the full 7k LaMAGIC validation set is costly and dominated by low\-performing circuits, our primary benchmark is6\-comp: 100 high\-efficiency samples spanning various conversion ratios\. To confirm the gains are not a selection artifact, we also evaluate6\-comp\-random\-100, 100 samples drawn uniformly from the original set \(Appendix[B\.4](https://arxiv.org/html/2607.13416#A2.SS4)\)\.

Evaluation metrics\.Our primary metric is success rate: the percentage of generated circuits meeting the preset target\(v∗,e∗\)\(v^\{\*\},e^\{\*\}\)\. For each target and search budgetnn, the method generates up tonncandidates and retains the best\. A circuit succeeds if its simulated conversion ratio and efficiency\(v,e\)\(v,e\), obtained via NGSPICE\(Nenzi and Vogt,[2011](https://arxiv.org/html/2607.13416#bib.bib11)\), both fall within tolerancettof the target:

\|v−v∗\|≤tand\|e−e∗\|≤t\.\|v\-v^\{\*\}\|\\leq t\\quad\\text\{and\}\\quad\|e\-e^\{\*\}\|\\leq t\.We report two variants: \(1\)tolerance\-based success rate, witht∈\{0\.01,0\.02,…,0\.10\}t\\in\\\{0\.01,0\.02,\\dots,0\.10\\\}, and \(2\)iteration\-wise success rate, which tracks success under strict tolerance \(t=0\.01t=0\.01\) as the number of generated candidates increases\. Candidates that fail to compile or simulate count as failures\. We additionally report mean squared errors \(MSEs\) for the voltage conversion ratio and efficiency to quantify deviation among valid circuits\.

Table 2\.Performance at thresholdt=0\.01t=0\.01with varying number of components\(7 → 10\)\. All methods use up to 100 Transformer generations\.![Refer to caption](https://arxiv.org/html/2607.13416v1/x5.png)Figure 5\.Comparison of generation results on validation sets with varying number of components \(7 → 10\), for Greedy, Sampling \+ Filtering \(S\+F\), MCTS\-Base, and our EXPLORE methods\.
### 4\.2\.Generation results on 6\-component circuit

Comparison with baselines\.For a fair comparison, we evaluate the best topology found by the different decoding algorithms when they use the same number of Transformer generations\. All methods are evaluated under the same success criterion on 6\-comp\.

Results are shown in Table[1](https://arxiv.org/html/2607.13416#S3.T1)\. Our method consistently outperforms all the other baselines on the 6\-comp validation set for various tolerance thresholds\. Overall, these results confirm that our algorithm indeed generates better topologies for the target voltage and efficiency\. As shown in Table[1](https://arxiv.org/html/2607.13416#S3.T1), EXPLORE largely outperforms the one\-shot generation methods, reaching a success rate of 0\.65 \(Ours\) versus 0\.33 \(S\+F\) when using the FM\-32k model at a tight tolerance of 0\.01 on 6\-comp\. S\+F uses the same number of transformer generations but is overall outperformed by EXPLORE\. Comparing with MCTS\-Base, this confirms that the LLM probability guidance is crucial in the node selection stage\. A runtime breakdown for our framework is also provided in Figure[4\(a\)](https://arxiv.org/html/2607.13416#S3.F4.sf1)\.

To illustrate the exploration efficiency of various decoding methods, Figure[4](https://arxiv.org/html/2607.13416#S3.F4)plots the strict\-tolerance success rate \(t=0\.01\) as a function of iteration count\. For EXPLORE, we fix the top\-k sampling budget at k=3 with a single beam \(b=1\) and sweep the P\-UCB exploration constant c\. We observe that c =1 yields faster gains in the very early iterations, while a larger c \(c=4\) drives more exploration and ultimately achieves the highest success\. In contrast, without the LLM token probability guidance, MCTS Baselines explores less effectively and converges to sub\-optimal results with other baseline sampling and filtering\.

We further sweep the p\-filtering thresholdppat fixedc=4c\{=\}4\(Figure[4](https://arxiv.org/html/2607.13416#S3.F4)\)\. Since p\-filtering auto\-commits tokens whose model probability already exceedspp, a smallerppskips more tokens and saves more budget per iteration\. The sweep reveals a clear trade\-off: aggressive filtering \(p=0\.7p\{=\}0\.7\) produces the fastest gains in the first few iterations, but skipping tokens the model is less confident about discards genuine decision content and plateaus lower, with the most aggressive setting \(p=0\.5p\{=\}0\.5\) capping at a success rate of 0\.37\. Settingp=0\.99p\{=\}0\.99auto\-commits only near\-certain structural tokens, preserving search quality and reaching the highest final success \(0\.51\) while still skipping 24–48% of token expansions\.

### 4\.3\.Generation results on 7–10 component circuit

A central claim of this work is that test\-time search scales more gracefully than one\-shot decoding as circuit complexity grows\. To test this, we retrain the baseline with 4K samples \(1K each from 6–9 components\) and build 7/8/9/10\-comp validation sets; details are in Appendix[B\.1](https://arxiv.org/html/2607.13416#A2.SS1)\. As shown in Figure[5](https://arxiv.org/html/2607.13416#S4.F5), all methods degrade as components increase from 7 to 10, but ours consistently leads across the 7/8/9/10 benchmarks\. Structured search \(EXPLORE and MCTS\-Base\) clearly outperforms the S\+F approaches, underscoring its importance for graph\-generation tasks such as circuit topology design\. Quantitatively \(Table[2](https://arxiv.org/html/2607.13416#S4.T2)\), EXPLORE achieves 10×\\times/13×\\times/4×\\timessuccess\-rate gains over the greedy baseline on 7/8/9\-comp, with up to 100×\\timeslower voltage MSE\.

Unseen 10\-component circuits\.The rightmost panel of Figure[5](https://arxiv.org/html/2607.13416#S4.F5)reports a 10\-component set entirely outside the 6–9 training range\. As expected, few valid circuits are generated, yet two points stand out: \(1\) even without pre\-training, EXPLORE still produces higher\-complexity circuits, indicating a scalability trend across component counts absent from training; and \(2\) its relative advantage persists, remaining the top method in this untrained regime\.

Overall, these results support our claim that test\-time search scales more effectively than baseline strategies as complexity grows, making it well suited to higher\-component and future large\-scale designs\. We stress that they reflect a*scalability trend*rather than practical readiness, as absolute success rates remain modest beyond 8 components\. Further results extending EXPLORE to other analog types \(op\-amps, bandgap references\) via AnalogGenie, and a discussion of MCTS as a data\-collection method, are deferred to Appendix[B\.2](https://arxiv.org/html/2607.13416#A2.SS2)and[B\.3](https://arxiv.org/html/2607.13416#A2.SS3)\.

## 5\.Conclusion

In this work, we propose EXPLORE, a search\-enhanced language model framework for analog circuit topology generation\. EXPLORE tightly integrates simulator\-guided Monte Carlo Tree Search \(MCTS\) with transformer\-based decoding, capitalizing on both the learned priors of pretrained models and the dynamic feedback of circuit simulators to navigate vast design spaces\. We adapt MCTS to the text\-based adjacency\-matrix formulation via PUCT\-style action priors from the language model, top\-kkexpansion, and p\-filtering that auto\-commits high\-confidence tokens so simulator budget concentrates on genuine decision points\.

Extensive experiments across varying data regimes and difficulty settings confirm that EXPLORE achieves higher success rates and lower error metrics than prior RL\-based search methods and language model decoding strategies such as sampling and filtering\. We further demonstrate its utility as a high\-quality data collection engine for scaling analog datasets in low\-coverage regimes\. Future work includes discovering more efficient circuits, generalizing to more complex analog designs, and developing search\-friendly formulations that reduce structural token overhead\.

###### Acknowledgements\.

This work was supported in part by NSF grant No\. 2112562\.

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## Appendix

## Appendix AFurther Explanation of methodologies

### A\.1\.P\-UCB node selection

To guide exploration during tree traversal, we extend the standard Upper Confidence Bound \(UCB\)\(Kocsis and Szepesvári,[2006](https://arxiv.org/html/2607.13416#bib.bib10)\)strategy by incorporating the token probability predicted by the language model\. The P\-UCB score for each child node is computed as:

e​x​p​l​o​r​a​t​i​o​n=log\(node\.visit\_count\)c​h​i​l​d\.v​i​s​i​t​\_​c​o​u​n​texploration=\\sqrt\{\\frac\{log\(node\.visit\\\_count\)\}\{child\.visit\\\_count\}\}s​c​o​r​e=e​x​p​l​o​i​t​a​t​i​o​n\+c×e​x​p​l​o​r​a​t​i​o​n∗c​h​i​l​d\.t​o​k​e​n​\_​p​r​o​b​a​b​i​l​i​t​yscore=exploitation\+c\\times exploration\*child\.token\\\_probabilitywheren​o​d​e\.v​i​s​i​t​\_​c​o​u​n​tnode\.visit\\\_countrecords the number of times the current \(parent\) node has been visited,e​x​p​l​o​i​t​a​t​i​o​nexploitationisc​h​i​l​d\.v​a​l​u​echild\.value, and language\-model probability are assigned at the parent to the action token that produced this child, i\.e\., the action priorP​\(a∣s\)P\(a\\mid s\)in classical PUCT terminology\. The hyperparametercccontrols the trade\-off between exploration and exploitation; in our experiments we sweepc∈\{0\.5,1,4\}c\\in\\\{0\.5,1,4\\\}\. The selection step picks the child with the highest score; the resulting selection, expansion, evaluation, and backpropagation steps are described in Section[3](https://arxiv.org/html/2607.13416#S3)\.

## Appendix BAdditional experimental setup and results

### B\.1\.Model training details and compute resources

TheFlan\-T5\-basemodel consists of 12 transformer layers in both the encoder and decoder\. Each layer includes key and value projections with a dimensionality of 64, a feed\-forward network with a hidden size of 2048, and employs 12 attention heads\. Overall, the model contains approximately 248 million parameters\.

To adapt the tokenizer for our specific application, we add custom tokens to its vocabulary\. For the FM task, the following tokens are introduced:<sep\>,<duty 0\.1\>,<duty 0\.3\>,<duty 0\.5\>,<duty 0\.7\>,<duty 0\.9\>,VIN,VOUT,GND,Sa,Sb,C,L,<no edge\>,<edge 1\>,<edge 2\>, and<both edges\>\.

Training is conducted on a machine equipped with eight NVIDIA A5000 GPUs\. The language model is trained over 30 epochs using the AdamW optimizer with an initial learning rate of3×10−43\\times 10^\{\-4\}\. A cosine learning rate schedule is applied with 300 warmup steps\. The batch size is set to 128, L2 regularization is applied with a strength of10−510^\{\-5\}, and the dropout rate is set to 0\.1\.

### B\.2\.Evaluation on Other Analog Component Types

![Refer to caption](https://arxiv.org/html/2607.13416v1/x6.png)Figure 6\.Device count distribution for the first 10000 generated circuits produced by AnalogGenie and AnalogGenie x EXPLORE\. Samples with zero devices correspond to invalid generations, including circuits with shorted connections or incomplete pin definitions\.Experimental Setup\.We follow the open\-source release of AnalogGenie, using its publicly available model checkpoint on HuggingFace to faithfully reproduce its analog circuit generation behavior\. A generated circuit is considered invalid if any device has incomplete pin connectivity \(e\.g\., an NMOS missing one or more of S/D/G/B\), or if an electrical short is detected, such as a direct connection between VDD and VSS\. We apply our framework using AnalogGenie’s original text\-based formulation and conduct experiments under the same generation setting\. The reward function is defined as a combination of circuit legality and device count, encouraging valid topologies while discouraging unnecessarily complex designs\.

Generation Results\.To evaluate the generality of the proposed formulation, we conduct an ablation study on AnalogGenie for generating additional analog components, including op\-amps and bandgap references\. Both AnalogGenie and AnalogGenie × EXPLORE are evaluated under the same generation budget \(10000 samples\) for a fair comparison\. As shown in Fig\.[6](https://arxiv.org/html/2607.13416#A2.F6), AnalogGenie produces a large fraction of zero\-device samples, corresponding to invalid circuits caused by pin shorts or incomplete connections\. In contrast, AnalogGenie × EXPLORE substantially reduces the invalid generation rate and shifts the distribution toward higher device counts\. This indicates improved topology exploration and more stable generation behavior, demonstrating that EXPLORE generalizes effectively to more complex analog circuit families\.

### B\.3\.MCTS as an effective data collection method

![Refer to caption](https://arxiv.org/html/2607.13416v1/x7.png)Figure 7\.The Vout vs efficiency distribution of our model collected dataset vs\. random connection generated dataset\.MCTS combined with generative models represents a powerful yet often overlooked approach for high\-quality data collection in complex design spaces\. Traditional random generation methods become exponentially ineffective as design complexity grows, with the vast topology search space severely diminishing the probability of discovering valid, high\-performance configurations\. Our empirical analysis quantifies this limitation: in a random generation of 10,000 6\-component circuits, 66\.13% exhibited efficiency below 2%, rendering them practically unusable for both application and training purposes\. In contrast, our MCTS\-based approach significantly mitigates this inefficiency problem, reducing the proportion of low\-performing circuits to just 18\.2%\. More importantly, our method substantially enhances the discovery of high\-quality designs, generating 23\.27% of circuits with efficiency exceeding 90%\-nearly three times higher than the 8\.3% achieved through random generation\. The complete efficiency distribution illustrated in Figure[7](https://arxiv.org/html/2607.13416#A2.F7)demonstrates this substantial quality difference\. This shows that beyond immediate circuit applications, our approach can facilitate an efficient mechanism for collecting a high\-quality dataset for automatic discovery of unconventional topology and enable further training for the language models\.

### B\.4\.Unbiased Random Evaluation on 6\-component

The 6\-comp subset is mined for high\-efficiency targets, which could in principle favor search\-based methods\. To rule out this selection bias, we evaluate on samples drawn uniformly at random from the full 7k LaMAGIC validation set\.

Table 3\.Performance on the6\-comp\-random\-100split \(100 samples drawn uniformly at random from the 7k LaMAGIC validation set\) at thresholdt=0\.01t=0\.01for both 1 k and 32 k training\-data budgets\. All methods use up to 100 Transformer generations\. EXPLORE retains the top success rate and lowest MSE, showing the main\-table gain is not an artifact of the 6\-comp selection\.We first report6\-comp\-random\-100, a 100\-sample uniform draw evaluated under the same metrics as the main 6\-comp table \(Table[3](https://arxiv.org/html/2607.13416#A2.T3)\)\. EXPLORE remains the top method at both training budgets, reaching 0\.84 success att=0\.01t\{=\}0\.01with the FM\-32k model versus 0\.70 for S\+F, with the lowest voltage and efficiency MSE\.

Table 4\.Performance on the6\-comp\-random\-500split \(500 samples drawn uniformly at random from the 7k LaMAGIC validation set\) at thresholdt=0\.01t=0\.01\. Greedy is taken as the first per\-target sample from the S\+F generations\. EXPLORE retains the top success rate and lowest MSE, confirming the main\-table gain is not an artifact of the 6\-comp selection\.To confirm the trend at larger scale, we further evaluate6\-comp\-random\-500\(Table[4](https://arxiv.org/html/2607.13416#A2.T4)\)\. EXPLORE is the top method att=0\.01t\{=\}0\.01\(0\.73 success vs\. 0\.59 for MCTS\-Base, 0\.48 for S\+F, and 0\.24 for Greedy\) and also attains the lowest voltage and efficiency MSE by more than an order of magnitude, confirming that the gain reported in Sec\.[4\.1](https://arxiv.org/html/2607.13416#S4.SS1)is not an artifact of the hard\-subset construction\. To keep the table comparable to the 6\-comp setting without separately rerunning argmax decoding on the random subset, the Greedy row is populated from the first per\-target sample of the S\+F generations\.

### B\.5\.Effect of LLM Probability Guidance

Within our tree structure framework, we incorporate probability guidance during node selection to leverage the LLM’s capabilities in directing tree\-based sampling\. To validate the effectiveness of this LLM\-provided probability guidance, we conducted a comparative analysis by modifying the MCTS baseline from standard UCB node selection to our version of P\-UCB node selection\. Figure[8](https://arxiv.org/html/2607.13416#A2.F8)confirms that the probability guidance from P\-UCB is useful\. However, our method still outperforms MCTS\(P\-UCB\) through the implementation of node shrinking, which effectively addresses the challenges posed by structural tokens in circuit formulation\. This advantage is particularly pronounced during the early exploration iterations\.

![Refer to caption](https://arxiv.org/html/2607.13416v1/x8.png)Figure 8\.Success rate of our method with MCTS \(Baseline\) and its MCTS\(P\-UCB\) variants\.