I designed a nibble-oriented CPU in Verilog to build a scientific calculator

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Summary

This project implements a fully functional scientific calculator in hardware using an FPGA, including a custom soft CPU, microcode firmware, and supporting tools. It provides a web-based simulator and open-source Verilog code.

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Cached at: 05/15/26, 06:33 PM

gdevic/FPGA-Calculator

Source: https://github.com/gdevic/FPGA-Calculator

From Gates to a Calculator

This project implements a fully functional scientific calculator in hardware using an FPGA. It includes a custom soft CPU, microcode firmware, and supporting tools.

For the full story, see the blog.

Try it in a web browser:

screenshot

Project Structure

FolderDescription
verilog/SystemVerilog source files for the CPU, ALU, I/O, and test benches
ucode/Microcode (firmware) for the soft CPU
quartus/Quartus project files for FPGA synthesis
modelsim/ModelSim simulation setup
Qt/Qt-based simulator and debugger (uses Verilator)
calctest/Command-line test harness for hardware verification (uses Verilator)
tools/Assembler and script compiler for the microcode
Pathfinding/Algorithm research and verification projects

Quick Start

The fastest way to try the calculator is to build the Qt simulator:

# From WSL2
cd /mnt/c/Projects/FPGA-Calculator/verilog
make qt

Then open Qt/Calculator.pro in Qt Creator and build for “Desktop Qt MSVC2022 64 Bit”.

See the verilog/ and Qt/ folders for detailed instructions.

Required Tools

Install these tools depending on your target:

ToolPurposeNotes
VerilatorVerilog simulationRequired for Qt simulator
QtDesktop/WebAssembly/Android appVersion 6.9+
QuartusFPGA synthesisVersion 13.0 SP1 for Cyclone II
ModelSimWaveform simulationOptional
Visual Studio 2022C++ compiler for QtCommunity Edition
Python 3Assembler and tools

Verilator Setup

Verilator runs in WSL2 (Windows Subsystem for Linux). The project source files reside on a Windows partition and are accessed from WSL2.

TargetVerilator VersionNotes
Desktop (Qt/MSVC)5.x (latest)Recommended
WebAssembly4.228Required (no thread support)
# Install prerequisites
sudo apt-get install build-essential autoconf flex libfl-dev bison

# Clone and build Verilator
git clone https://github.com/verilator/verilator
cd verilator
git checkout v5.042    # For Desktop, or v4.228 for WebAssembly
autoconf
./configure
make -j8
make test

# Set environment (add to .bashrc for persistence)
export VERILATOR_ROOT=$(pwd)

Optionally install GtkWave for viewing waveforms:

sudo apt install gtkwave

Build Targets

TargetCommandDescription
Qt Simulatormake qt in verilog/Build for Qt desktop application
Calctestmake calctest in verilog/, then make in calctest/Command-line test harness
ModelSimmake test_self in verilog/CPU self-test for ModelSim
FPGA Hardwaremake revB in verilog/Assemble microcode for RevB board

See the README files in each subfolder for detailed build instructions:

Pathfinding Projects

Independent research and verification projects:

FolderDescription
Pathfinding/Proto/BCD arithmetic golden reference for hardware verification (submodule)
Pathfinding/Proof/Proofs of concept for complex operations using basic arithmetic
Pathfinding/Methods/C++ implementations of calculator algorithms (deprecated)
Pathfinding/Input/Numerical input state machine simulation
Pathfinding/Mockup/Keyboard layout design and user interaction testing

License

This project is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.

You are free to:

  • Share - copy and redistribute the material in any medium or format
  • Adapt - remix, transform, and build upon the material

Under the following terms:

  • Attribution - You must give appropriate credit and indicate if changes were made
  • NonCommercial - You may not use the material for commercial purposes
  • ShareAlike - Contributions must be distributed under the same license

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