China’s DFSX Offers 2x The Memory Bandwidth Of NVIDIA’s GB200

# China’s DFSX Offers 2x The Memory Bandwidth Of NVIDIA’s GB200 NVL72 System With a 14nm SuperNode That Skips Microbumps for Vertical Compute-Memory Towers Source: [https://wccftech.com/chinas-dfsx-offers-2x-the-memory-bandwidth-of-nvidias-gb200-nvl72-system-with-a-14nm-supernode-that-skips-microbumps-for-vertical-compute-memory-towers/](https://wccftech.com/chinas-dfsx-offers-2x-the-memory-bandwidth-of-nvidias-gb200-nvl72-system-with-a-14nm-supernode-that-skips-microbumps-for-vertical-compute-memory-towers/) China's Dongfang Suanxin \(DFSX\) is on a quest to prove that memory bandwidth, and not an incessant obsession with node miniaturization, is the key to unlocking sizable economies of scale for AI workloads, as demonstrated by its DF1000 and the upcoming DF2000 chips, typically arrayed within TY64 SuperNodes to give NVIDIA's GB200 NVL72 system a run for its money\. ## A DFSX TY64 SuperNode, made up of 14nm DF2000 chips, will offer a memory bandwidth of 960TB/s vs\. just 576TB/s for NVIDIA GB200 NVL72 systems For the benefit of those who might not be aware, DFSX's DF1000 chip is fabricated using the mature 14nm process, but sports a novel[3D near\-memory compute architecture](https://www.chinadaily.com.cn/a/202607/28/WS6a6802f4a310986e2b4679f3.html), where memory is stacked directly on top of the compute layer and connected via 3D wafer\-level hybrid bonding, which melds the copper pathways of the two layers, completely eliminating microbumps or wires, and acts like tens of millions of ultra\-fast vertical elevators instead of a single horizontal highway\. In contrast, the DF2000 chip, which is expected to debut in Q4 2026 on the 14nm node, takes things a step further\. Instead of stacking just a single memory layer on top of the compute layer, the DF2000 combines multiple stacked memory\-compute towers next to each other on a base foundation in a technique that DFSX calls 3\.5D Infinity Chiplet layout\. The chip essentially replaces basic storage layers with a custom\-engineered[3D Dynamic Random\-Access Memory \(DRAM\)](https://wccftech.com/china-develops-first-3-5d-infinity-chiplet-3d-dram-tech-as-it-tackles-external-constraints/)layout, dramatically increasing the quantum of temporary data that can be held directly inside its structure\. > What does DFSX chips look like\. Here is a showcase of how effective 3D hybrid bonding approach can improve the inference speed\. DF2000 using multiple logic chiplet \+ layers of DRAM can achieve 1\.6T interconnect \+ 15 TB/s memory bandwidth w/ 1000T BF16 compute this year\.[pic\.twitter\.com/Ly3Ou82vdm](https://t.co/Ly3Ou82vdm) — tphuang \(@tphuang\)[August 1, 2026](https://x.com/tphuang/status/2083643170525528440?ref_src=twsrc%5Etfw) Basically, DFSX is trying to solve a persistent problem for AI workloads, where the GPUs remain idle most of the time as they wait for data to arrive from memory layers\. DFSX is postulating that memory wall \- not node miniaturization \- is the biggest throttle here\. And, we now have numbers to back up these claims\. For instance, each DF2000 chip offers a bandwidth of 15TB/s\. When stacked in a TY64 SuperNode format, the total memory bandwidth increases to 960TB/s\. In contrast, NVIDIA's GB200 NVL72 system offers a total memory bandwidth of just[576TB/s](https://www.nvidia.com/en-us/data-center/gb200-nvl72/)\! Of course, the difference between a 4nm chip and a 14nm one becomes apparent when one looks at their respective BF16 scores, where the DF2000\-based TY64 SuperNode offers 64 PFLOPS of BF16 compute vs\.[360 PFLOPS](https://polarise.eu/ai-factories/hw/gb200/)for the GB200 NVL72 system\. But, DFSX is banking on its 2x memory bandwidth to paper over any lacunae in the raw compute power of the DF2000\-based TY SuperNode\. > As flagship LLM continue to get larger, the primary throughput limiting factor has long shifted from per chip compute to system integration, size of memory, memory bandwidth, interconnect speed & all the supply chain around it\. Start of multi\-thread series of why FLOPS is wrong…[https://t\.co/95h6Ri2B76](https://t.co/95h6Ri2B76)[pic\.twitter\.com/NEudRMbV5J](https://t.co/NEudRMbV5J) — tphuang \(@tphuang\)[August 1, 2026](https://x.com/tphuang/status/2083639895193534579?ref_src=twsrc%5Etfw) Basically, DFSX believes that FLOPS is the wrong metric to focus on when it comes to AI workloads, with memory throughput constituting the most important metric\. Do note that DF3000 chip is expected to offer a memory bandwidth of 20TB/s or 1,280TB/s when arrayed within the TY64 SuperNode\. Meanwhile, NVIDIA's Vera Rubin NVL72 system offers a total memory bandwidth of[1,580TB/s](https://lambda.ai/vr-200), which is only 23 percent greater than what the DF3000\-based TY64 SuperNode will offer\. [](https://wccftech.com/author/rohail/) **About the[author](https://wccftech.com/author/rohail/):**Writing is my one incontrovertible passion\. Over the past six years, he has authored over 2,200 distinct articles on financial and tech\-related topics, spanning nearly 1 million words\. And he has been a member of Wcctech[mobile](https://wccftech.com/topic/gadgets/)team since 2025\. As an alumnus of the University of Toronto, Rotman Commerce Program, I bring nuance, in\-depth knowledge, and a unique perspective to every topic that I cover\. When I'm not writing, I'm traveling the world, exploring hidden confectionaries and restaurants as an aspiring food connoisseur\. Follow[Wccftech on Google](https://profile.google.com/cp/Cg0vZy8xMWM3NDB2MmIyGgA)to get more of our news coverage in your feeds\.