@QVHenkel: On many high-speed designs it is necessary to have a ground-plane void underneath large pads to minimize the local impe…
Summary
A user describes using GPT-6 to create a script that automates PCB design simulations with openEMS to optimize ground-plane voids for impedance control, planning to port it to palace EM for faster parallel processing.
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Cached at: 09/07/26, 11:12 PM
On many high-speed designs it is necessary to have a ground-plane void underneath large pads to minimize the local impedance dip. I´ve used GPT-6 to create a script that reads the layerstack information through the Altium PCB API, isolate the target net- and pad class, creates an openEMS simulation, run the simulation to find the pad void size that does not create an impedance dip compared to the trace that is attached to the pad and ultimately apply the calculated GND void expansion value to all pads in a user-defined net class. Currently all pads still receive the same expansion value. I will port the setup to use palace EM in order to automatically solve the expansion values for all different pad sizes/shapes in parallel which should be much faster than openEMS.
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