智能体能否通过更高层次的抽象设计更好的芯片？

# Can Agents Design Better Chips with a Higher Level Abstraction?
Source: [https://arxiv.org/html/2609.21157](https://arxiv.org/html/2609.21157)
Conference:IEEE/ACM International Conference on Computer\-Aided Design; November 08–12, 2026; San Jose, CA, USAIEEE/ACM International Conference on Computer\-Aided Design \(ICCAD ’26\), November 08–12, 2026, San Jose, CA, USADOI:[10\.1145/3831252\.3847810](https://doi.org/10.1145/3831252.3847810)ISBN:979\-8\-4007\-2873\-0/2026/11CCS:Hardware Electronic design automation\(Invited Paper\)

,Yang ZouAffiliation:UCLA,Los Angeles,CA,USAemail:[willz0123@g\.ucla\.edu](mailto:[email protected]),Yizhou SunAffiliation:UCLA,Los Angeles,CA,USAemail:[yzsun@cs\.ucla\.edu](mailto:[email protected])andJason CongAffiliation:UCLA,Los Angeles,CA,USAemail:[cong@cs\.ucla\.edu](mailto:[email protected])

© cc

###### Abstract\.

Large Language Model \(LLM\) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL\. We ask whether agents can design better chips by leveraging higher\-level abstractions\. We compare Direct RTL Design, Agent\-based HLS Design, Post\-Compiler HLS Refinement, and Post\-HLS RTL Refinement, and combine Agent\-based HLS Design with Post\-HLS RTL Refinement as Agent\-based HLS with RTL Refinement \(AHRR\)\. We use FPGAs as a practical, easy\-to\-deploy platform for end\-to\-end evaluation, but note that the design\-flow tradeoffs we study are largely independent of the target technology\. Across a diverse 11\-tasks benchmark suite, AHRR achieves a 2\.6×\\timesgeometric\-mean speedup over Direct RTL Design across our benchmark suite\. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower\-level optimization opportunities\. Together, these results make AHRR a promising workflow for agentic chip design\. The code and evaluation artifacts are available at https://github\.com/ZijD/AHRR\.

###### Keywords:

High\-level synthesis, LLM agents, FPGA

††cc\-license:by## 1\.Introduction

Figure 1\.The four design flows studied in this paper\. In \(i\) Direct RTL Design, the agent writes RTL directly from the specification\. In \(ii\) Agent\-based HLS Design, the agent writes HLS C\+\+ and Vitis HLS generates RTL\. In \(iii\) Post\-HLS RTL Refinement, the agent further refines HLS\-generated RTL\. In \(iv\) Post\-Compiler HLS Refinement, a domain\-specific compiler generates the initial HLS C\+\+, which the agent further refines\.Flow DiagramRecent advances in Large Language Models \(LLMs\) and LLM\-based coding agents have created growing interest in applying them to chip design\. LLM agents have been explored for hardware generation, debugging, verification and optimization\([Liu et al\., 2023](https://arxiv.org/html/2609.21157#bib.bib10);[Pinckney et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib11);[Ho et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib17);[Zhao et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib25);[Bai et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib26)\), and it is already applied in commercial design\(jalape~no\)\.

However, RTL is not the only interface between an agent and the hardware design process\. It has been widely used in manual designs as it provides cycle\-accurate specification\. In contrast, High\-Level Synthesis \(HLS\)\([Cong et al\., 2011](https://arxiv.org/html/2609.21157#bib.bib2);[Cong et al\., 2022](https://arxiv.org/html/2609.21157#bib.bib4)\)lets designers express computation in C/C\+\+ while delegating scheduling, pipelining, and RTL generation to a compiler, and domain\-specific HLS frameworks\([Wang et al\., 2021](https://arxiv.org/html/2609.21157#bib.bib20);[Chi et al\., 2018](https://arxiv.org/html/2609.21157#bib.bib21);[Basalama and Cong, 2025](https://arxiv.org/html/2609.21157#bib.bib19)\)raise the abstraction further by providing and optimizing parameterized architecture templates\. Agents have begun to work at the HLS level as well\([Zou et al\., 2026](https://arxiv.org/html/2609.21157#bib.bib34);[Wang et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib24);[Prakriya et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib9)\), but whether the abstraction itself helps an agent to produce a higher quality design is less clear\. Direct RTL generation gives the agent full control, whereas HLS and domain\-specific compilers restrict the design space to a usually high\-quality subset\. The two approaches can also be combined in multiple ways: \(i\) Direct RTL Design, where an agent creates RTL directly, \(ii\) Agent\-based HLS Design, where an agent optimized HLS C/C\+\+ code and then relies on HLS tools to generate RTL, \(iii\) Post\-HLS RTL Refinement, where an agent further optimizes the HLS\-generated RTL, and \(iv\) Post\-Compiler HLS Refinement, where a domain\-specific compiler first generates an HLS design that is further refined by an agent, with the resulting RTL serving as the input to flow \(iii\)\. We refer to flows \(ii\)\+\(iii\) as AHRR: Agent\-based HLS with RTL Refinement \(Figure[7](https://arxiv.org/html/2609.21157#S5.F7)\), where the agent first designs at the HLS level and then refines the generated RTL\.

These alternatives points to a fundamental question:*can agents design better chips when operating at a higher level of abstraction using HLS, and how?*

Our contributions are:

- •We systematically study LLM\-based chip\-design agents across RTL, HLS, and compiler\-assisted design flows\.
- •We show our proposed AHRR outperform Direct RTL by2\.6×2\.6\\timesgeometric\-mean\.
- •We further study Post\-Compiler HLS Refinement, showing that agents can improve both HLS\-generated RTL and compiler\-generated HLS\.

Evaluation across these design flows \(Figure[1](https://arxiv.org/html/2609.21157#acmlabel1)\) show that agents can design better chips by leveraging HLS and domain\-specific HLS compilers that encode human design knowledge, combining machine and human intelligence\.

## 2\.Background

Table 1\.The 11\-task benchmark suite spans LLM inference, agentic memory, robotics, and GEMM\. Selected tasks use fixed\-point arithmetic to avoid floating\-point IP\. Dynamic dimensions are preserved when possible, and some workloads are scaled down to reduce RTL simulation time\.HLS raises hardware design from RTL to C/C\+\+ and reduces the verification burden\([Cong et al\., 2011](https://arxiv.org/html/2609.21157#bib.bib2);[Cong et al\., 2022](https://arxiv.org/html/2609.21157#bib.bib4)\)\. Most agentic chip\-design work targets RTL\([Liu et al\., 2023](https://arxiv.org/html/2609.21157#bib.bib10);[Pinckney et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib11);[Ho et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib17);[Zhao et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib25);[Thakur et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib14)\), while recent work explores HLS for pragma insertion, refactoring, and design\-space exploration\([Xiong et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib12);[Collini et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib15);[Xu et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib16);[Zou et al\., 2026](https://arxiv.org/html/2609.21157#bib.bib34);[Wang et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib24);[Prakriya et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib9)\)\. Domain\-specific HLS compilers generate optimized architectures for particular computation patterns\([Wang et al\., 2021](https://arxiv.org/html/2609.21157#bib.bib20);[Chi et al\., 2018](https://arxiv.org/html/2609.21157#bib.bib21);[Basalama and Cong, 2025](https://arxiv.org/html/2609.21157#bib.bib19);[Ye et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib22);[Ye and Chen, 2025](https://arxiv.org/html/2609.21157#bib.bib23);[Chen et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib3);[Ye et al\., 2022](https://arxiv.org/html/2609.21157#bib.bib6);[Pouget et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib7)\)\. We use AutoSA and StreamHLS as starting points\. Our agents follow the standard iterative coding\-agent loop\([Yao et al\., 2022](https://arxiv.org/html/2609.21157#bib.bib13);[Shinn et al\., 2024](https://arxiv.org/html/2609.21157#bib.bib8);[Novikov et al\., 2025](https://arxiv.org/html/2609.21157#bib.bib18)\), under a fixed round budget and a hidden testbench\.

## 3\.Methodology

In this section, we describe the common agent loop, the four design flows in Figure[1](https://arxiv.org/html/2609.21157#acmlabel1), and the hidden testbench\.

#### Specification\-driven design\.

In Direct RTL Design \(i\) and Agent\-based HLS Design \(ii\), the agent starts from the same task specification, task package, and evaluation harness\. The task package includes a correct, unoptimized C\+\+ implementation, one test stimulus, and a fixed interface contract\. The agent then designs the accelerator either directly in RTL or in HLS C\+\+\. Within each round, the agent has up to one hour to develop and submit a candidate design\. The evaluation harness records correctness on the hidden testbench, simulated cycle count, post\-route clock period, and resource utilization\. We use the open\-source coding agentpi\([Mario Zechner and contributors, 2026](https://arxiv.org/html/2609.21157#bib.bib33)\)without modification\. The agent’s session is carried across rounds, and each round’s prompt reports the previous three rounds of evaluation results\. We keep the prompt minimal, specifying only the optimization objective, resource budget, interface requirements, and submission protocol\. In the RTL flow, the agent additionally receives the required port specification and, for AXI\-based tasks, a provided AXI wrapper around the kernel\.

#### Refinement from tool\-generated designs\.

Flows \(iii\) and \(iv\) start from an existing implementation rather than only the task specification\. In Post\-Compiler HLS Refinement \(iv\), the agent starts from HLS C\+\+ generated by a domain\-specific compiler, such as AutoSA\([Wang et al\., 2021](https://arxiv.org/html/2609.21157#bib.bib20)\)or StreamHLS\([Basalama and Cong, 2025](https://arxiv.org/html/2609.21157#bib.bib19)\)\. In Post\-HLS RTL Refinement \(iii\), it starts from Verilog produced by Vitis HLS, either from an Agent\-based HLS design or a refined compiler\-generated HLS design\. Apart from the starting artifact and abstraction level, the optimization loop and evaluation procedure remain unchanged\.

*Hidden testbench\.*The public testbench provides a single stimulus for local development, while correctness is evaluated with a hidden testbench containing broader inputs and specification\-derived corner cases\. We strengthen each testbench until the C\+\+ reference reaches100%100\\%branch coverage, and additionally measure statement and branch coverage on the reference RTL implementation\.

Table 2\.Parameters fixed across experiments\.

## 4\.Evaluation

Table 3\.Comparison of the specification\-driven design workflows\. Speedups are relative to Direct RTL Design on the same task and model\. Geometric means include only pairs with a valid Direct RTL baseline;nndenotes the number of included pairs\. AHRR hasn=13n=13because Post\-HLS RTL Refinement was not evaluated on the two GEM1 \(3 AXI\) cases\.\(i\) Direct RTL Design\(ii\) Agent\-based HLS Design\(ii\)→\\rightarrow\(iii\)AHRRTaskModelmsspeedupmsspeedupmsspeedupGEM1 \(3 AXI\)gemini2\.191\.00×\\times0\.405\.43×\\times––gpt1\.311\.00×\\times0\.552\.40×\\times––LLM1gemini1\.291\.00×\\times0\.433\.02×\\times0\.433\.02×\\timesgpt2\.541\.00×\\times0\.475\.37×\\times0\.435\.87×\\timesLLM2gemini×\\times0\.20–0\.20–gpt1\.231\.00×\\times0\.216\.00×\\times0\.216\.00×\\timesMEM1gemini×\\times7\.44–7\.44–gpt5\.261\.00×\\times5\.271\.00×\\times5\.251\.00×\\timesMEM2gemini×\\times0\.37–0\.37–gpt0\.651\.00×\\times0\.371\.75×\\times0\.322\.02×\\timesMEM3gemini3\.621\.00×\\times3\.501\.03×\\times3\.501\.03×\\timesgpt3\.501\.00×\\times3\.501\.00×\\times3\.501\.00×\\timesROB1gemini6\.161\.00×\\times0\.5012\.35×\\times0\.4513\.82×\\timesgpt0\.301\.00×\\times0\.530\.56×\\times0\.330\.90×\\timesROB2gemini35\.381\.00×\\times6\.375\.56×\\times6\.225\.69×\\timesgpt9\.221\.00×\\times2\.613\.53×\\times2\.204\.19×\\timesROB3gemini0\.021\.00×\\times0\.011\.73×\\times0\.011\.95×\\timesgpt0\.011\.00×\\times0\.010\.54×\\times0\.002\.09×\\timesgeo\. mean1\.00×\\times\(nn=15\)2\.31×\\times\(nn=15\)2\.62×\\times\(nn=13\)In this section, we evaluate how the abstraction level affects agentic chip design\. We first compare Direct RTL Design and Agent\-based HLS Design to isolate the benefit of HLS\. We then evaluate Post\-HLS RTL Refinement and Post\-Compiler HLS Refinement\.

### 4\.1\.Experimental Setup

We run Gemini 3\.1 Pro at high reasoning effort and GPT\-5\.6\-sol at extra\-high effort under the samepiharness with every parameter fixed \(Table[2](https://arxiv.org/html/2609.21157#S3.T2)\)\.

A design is valid if it passes the hidden testbench, routes successfully, and stays within the resource ceiling\. We compute execution time as the simulated cycle count multiplied by the maximum of the post\-route clock period and the target clock period\. All reported speedups are measured relative to execution time on the same task\. Each experiment runs once\. Table[1](https://arxiv.org/html/2609.21157#S2.T1)lists the eleven tasks\. For GEM1, we have two variants, one with naive sequential design with 3 AXI masters \(A,B,C\) for RTL v\.s\. HLS comparison, and the other with generated by AutoSA with 12 AXI masters\.

### 4\.2\.Overview: Design\-Flow Comparison

Table[3](https://arxiv.org/html/2609.21157#S4.T3)compares the specification\-driven workflows\. Agent\-based HLS Design achieves a 2\.31×\\timesgeometric\-mean speedup over Direct RTL Design\. Extending it with Post\-HLS RTL Refinement to form AHRR increases the speedup to 2\.62×\\times\. We separately evaluate Post\-Compiler HLS Refinement in Section[4\.5](https://arxiv.org/html/2609.21157#S4.SS5)\.

### 4\.3\.Agent\-based HLS vs\. Direct RTL

We first isolate the effect of abstraction by giving the same agent the same task specification and asking it to design in either RTL or HLS, corresponding to flows \(i\) and \(ii\)\.

Figure 2\.Performance and resource comparison of Agent\-based HLS Design and Direct RTL Design\. With HLS, state\-of\-the\-art agents achieve a 2\.31×\\timesgeometric\-mean speedup over direct RTL design\.Performance and resource comparison of Agent\-based HLS Design and Direct RTL Design\.With the HLS tool available, the agent can express parallelism through loop transformations and pragmas\. In RTL, the same agent must realize these structures explicitly and often produces a narrower datapath\. This demonstrates that HLS tools carry distilled design knowledge that agents can leverage\. We provide a detailed case study in Figure[4](https://arxiv.org/html/2609.21157#S5.F4)\.

Direct RTL Design may still win when the design is small\. The two cases where RTL outperforms HLS are both on small kernels, ROB1 and ROB3, and by 1\.78×\\timesand 1\.85×\\timesrespectively\. When the kernel state fits in registers, the RTL flow can place it there directly, while HLS can only express the intent through binding pragmas\. We also note that we use naive agent for both Agent\-based HLS Design and Direct RTL Design, and a simple prompt update may significantly improve/degrade performance on both sides\.

We next ask whether the agent can combine both advantages by refining the HLS\-generated RTL\.

### 4\.4\.Post\-HLS RTL Refinement

We next apply Post\-HLS RTL Refinement to the Verilog generated from the best Agent\-based HLS design\. The agent continues optimization directly at the RTL level\.

Across the sixteen valid cases, Post\-HLS RTL Refinement improves performance by 1\.17×\\timesgeometric mean over its HLS\-generated RTL starting point\.

Figure 3\.Per\-round progress of Post\-HLS RTL Refinement, normalized to the HLS\-generated RTL that seeds each experiment\. All axes are oriented so that higher is better\. LUT and DSP savings are shown alongside speedup to capture the tradeoff between area and performance\. We also include SHL1/SHL2 to illustrate that Post\-HLS RTL Refinement becomes challenging when simulation time is long\.post hls rtl optimizationFigure[3](https://arxiv.org/html/2609.21157#S4.F3)isolates the effect of Post\-HLS RTL Refinement, showing the per\-round progress of each agent\. We use throughput/latency as the primary objective and resource usage as the secondary objective\. On LLM1, MEM1/2/3, and ROB2, agents make incremental improvements over the HLS\-generated RTL\. On ROB1 and ROB3, the agents achieve22\-4×4\\timesspeedups through complete rewrites, consistent with the results in Figure[2](https://arxiv.org/html/2609.21157#S4.F2)\. On LLM2 and MEM3, GPT and Gemini also substantially reduce resource usage with only a few lines of RTL edits, which we examine in Section[5\.3](https://arxiv.org/html/2609.21157#S5.SS3)\.

Most successful rounds make local edits rather than large rewrites, and these edits usually change the cycle count by less than 1\.15×\\times\. Every larger latency improvement comes from a complete rewrite, where the agent discards the HLS\-generated RTL and writes a new implementation\.

### 4\.5\.Post\-Compiler HLS Refinement

We finally study a stronger starting point, where a domain\-specific compiler first generates the HLS design and the agent refines the generated C\+\+\. Table[4](https://arxiv.org/html/2609.21157#S4.T4)reports the results\. On SHL2, Gemini and GPT improve StreamHLS by 3\.3×\\timesand 1\.7×\\times\. On GEM1, both improve AutoSA by 1\.3×\\timesand 1\.2×\\timeswhile changing the cycle count by less than 2%, with the gains coming from improved timing\. Gemini changes storage bindings \(”bind\_storage type=ram\_2p impl=lutram“\) and FIFO depths \(2\-\>4\), while GPT restructures control and the PE datapath\. In both cases, the agents incrementally improve an already optimized compiler\-generated HLS design, showing that useful optimization opportunities remain after compiler optimization\.

Table 4\.Post\-Compiler HLS Refinement relative to the domain\-specific compiler baseline, reported as Gemini / GPT\. We use StreamHLS for SHL1/SHL2 and AutoSA for GEM1\.For SHL1, neither agent improves upon the compiler\-generated design\. This is not necessarily an intrinsic limitation of the agents\. The initial compiler\-generated design already requires simulation time close to our timeout limit, leaving little room for iterative exploration\. A better evaluation harness could use HLS latency estimates during optimization and reserve full simulation for validation, which we leave to future work\.

## 5\.Case Study

In this section, we examine the design and agent decisions that most clearly reveal the role of high\-level abstractions in agentic chip design\. We first show how Agent\-based HLS Design can scale designs efficiently, illustrating how abstractions expose useful design knowledge\. We then show that compilers translating these abstractions can still leave inefficiencies that agents can identify and improve\. Finally, we examine how Post\-HLS RTL Refinement can improve timing and area beneath the HLS\-generated design\.

### 5\.1\.High Level Abstractions Distill Design Knowledge for Agent

Figure[4](https://arxiv.org/html/2609.21157#S5.F4)shows ROB1, greedy non\-maximum suppression\. Object detectors often produce multiple high\-scoring, overlapping candidate boxes for the same object\. Non\-maximum suppression \(NMS\) reduces these duplicates by repeatedly selecting the highest\-scoring remaining box and suppressing candidates whose intersection\-over\-union \(IoU\) with it exceeds a threshold\([Bodla et al\., 2017](https://arxiv.org/html/2609.21157#bib.bib28)\)\. ROB1 applies greedy NMS to up to 8192 candidate boxes, keeps at most 512, and uses a 50% IoU threshold\. For each retained box, the design performs an argmax pass to select the next box and a suppression pass to remove overlapping candidates\. This requires roughly2​K​N2KNbox visits forKKretained boxes amongNNcandidates, making the number of boxes processed per cycle the main latency bottleneck\.

Figure 4\.Abstractions distill design knowledge for agents\. On the left, the same agent implements ROB1 through HLS and direct RTL Design\. The HLS design uses two pragmas to produce 256\-way parallelism, while the direct RTL design achieves only 32/8\-way parallelism despite requiring more Verilog than HLS C\+\+\. On the right, across six tasks, the weaker model nearly matches the stronger model when both operate through HLS\.case study 1With HLS, the agent asked for that degree of parallelism in one pragma each, anARRAY\_PARTITIONinto 256 banks and aPIPELINEat one iteration per cycle, and Vitis HLS supplied what the request implies: a 256\-port read, a log\-depth comparison tree and the pipeline registers between its levels, in 43914 lines of Verilog\. The same agent writing Verilog directly built a 32\-lane argmax and an 8\-lane suppression sweep in 378 lines and 15 pipeline stages, reading one 512\-bit word per cycle from the memory port\. Its design runs 1\.86M cycles against 127K, with 5454 LUTs against HLS\-generated RTL’s 118K\. The right panel of Figure[4](https://arxiv.org/html/2609.21157#S5.F4)shows the same effect across models: on the six tasks where all 4 pairs of \(GPT/Gemini\)x\(HLS/RTL\) succeed, the weaker model reaches 0\.40×\\timesthe speedup of the stronger with direct RTL and 0\.95×\\timeswith HLS\. This demonstrate that HLS simplify the effort of design optimization\.

### 5\.2\.Agents Recover Inefficiencies Left by Compiler Heuristics

Figure 5\.Agents recover inefficiencies left by compiler heuristics\. The StreamHLS design passes through Post\-Compiler HLS Refinement and Post\-HLS RTL Refinement\. At HLS level, Four whole tensors are rewritten to two rows and a window, reducing cycle count by 61%\. At RTL level, a multiplier with a pinned operand becomes a lookup table, reducing the clock period by 9% at unchanged cycle count\.case study 2Figure[5](https://arxiv.org/html/2609.21157#S5.F5)follows the SHL2 design through Post\-Compiler HLS Refinement \(iv\) and Post\-HLS RTL Refinement \(iii\)\. StreamHLS generates four local arrays totaling 405K floating\-point values and adds an extra stage to fill a padded copy before the convolution reads it\. This illustrates a common limitation of source\-to\-source compilers: even when the abstraction points optimization in the right direction, code generation still relies on fixed heuristics that may not generalize across designs\.

This is where agents can complement compiler automation\. With Post\-Compiler HLS Refinement, the agent kept two rows of line buffer and a 3×\\times3 window, 1842 floating points in all, and deleted the padding stage\. The cycle count fell from 539726 to 209297 and the block RAM from 224 to 2\.

The same design also benefits from Post\-HLS RTL Refinement\. The agent identifies two multiplier modules whose second operands are already constant in the generated RTL and replaces them with lookup tables\. The clock period drops from 4\.20 to 3\.82 ns with no change in cycle count\.

This case illustrates an ideal division of optimization, where compilers and higher\-level abstractions make the “giant steps” and agents recover case\-specific “baby steps” with surgical precision\.

### 5\.3\.Agents optimize timing and area beneath the HLS schedule

Figure[6](https://arxiv.org/html/2609.21157#S5.F6)traces two designs through Post\-HLS RTL Refinement \(iii\)\. At the HLS level, both computations are expressed compactly, but the generated RTL exposes lower\-level implementation choices that the agent can further improve\.

Figure 6\.Agents optimize timing and area beneath the HLS schedule: on MEM3, moving the min/max selection before multiplication cuts DSP usage and cuts LUTs by 2\.2×\\timeswithout changing the cycle count\. On ROB1, rewriting the comparison removes a subtractor from the critical path and reduces the clock period from 3\.60 to 3\.31 ns\.case study 3On MEM3, the HLS design computesmax⁡\(q⋅𝑚𝑖𝑛,q⋅𝑚𝑎𝑥\)\\max\(q\\cdot\\mathit\{min\},q\\cdot\\mathit\{max\}\)for each of 32 vector elements\. Vitis HLS implements this with two multipliers per element and selects the larger product, using 64 DSPs in total\. Gemini observes that the sign ofqqalone determines whether𝑚𝑖𝑛\\mathit\{min\}or𝑚𝑎𝑥\\mathit\{max\}should be used, and moves this selection before the multiplication\. This reduces the design to one multiplier per element, cutting DSP usage from 64 to 32 and LUT usage from 4,868 to 2,228, while keeping the cycle count nearly unchanged\. The clock period also improves from 3\.14 to 2\.83 ns\.

On ROB1, the generated RTL implements the 50% intersection\-over\-union comparison as𝑢𝑛𝑖𝑜𝑛<2⋅𝑖𝑛𝑡𝑒𝑟𝑠𝑒𝑐𝑡𝑖𝑜𝑛\\mathit\{union\}<2\\cdot\\mathit\{intersection\}, where𝑢𝑛𝑖𝑜𝑛=a\+b−𝑖𝑛𝑡𝑒𝑟𝑠𝑒𝑐𝑡𝑖𝑜𝑛\\mathit\{union\}=a\+b\-\\mathit\{intersection\}\. This places a multiplier, a 33\-bit subtractor, and a comparator on the critical path\. GPT instead rewrites the equivalent condition asa\+b<3⋅𝑖𝑛𝑡𝑒𝑟𝑠𝑒𝑐𝑡𝑖𝑜𝑛a\+b<3\\cdot\\mathit\{intersection\}, removing the subtractor from the path\. The clock period improves from 3\.60 to 3\.31 ns, meeting the 3\.33 ns target, with the same cycle count and 4% fewer LUTs\.

These examples show another useful division of optimization\. HLS captures the high\-level computation and generates a complete implementation, while the agent can inspect the resulting RTL and recover case\-specific opportunities in resource mapping, arithmetic structure, and timing that only become explicit after RTL generation\.

### 5\.4\.Recommended Flow

Our results suggest combining Agent\-based HLS Design with Post\-HLS RTL Refinement as a promising flow for agentic chip design, which means that starting starting with a design specification in natural language or some high\-level executable language, an agent generates optimized HLS C/C\+\+ code, and the further inspects the generated RTL code by an HLS tool for further refinement at the RTL level\. We name it the AHRR Flow\. Figure[7](https://arxiv.org/html/2609.21157#S5.F7)illustrates the AHRR flow\.

Figure 7\.The proposed AHRR workflow\.The key strength of AHRR is its combination of*architectural leverage*from HLS and*cycle\-accurate control*at RTL\. At the HLS level, the agent can efficiently explore broad architectural transformations through compact C/C\+\+ changes and compiler directives\. After RTL generation, the same agent can inspect the generated implementation and further refine timing, storage, and datapath decisions that only become explicit at the lower level\. These two stages are complementary: Agent\-based HLS Design already achieves a 2\.31×\\timesgeometric\-mean speedup over Direct RTL Design, while subsequent RTL refinement increases the speedup to 2\.62×\\times\. This ability to operate effectively on both sides of the HLS compiler boundary makes AHRR particularly promising for agentic chip design\.

## 6\.Conclusion

In this study, through extensive evaluation using the latest commercial AI agents in conjunction with state\-of\-the\-art HLS tools, we conclude that the AHRR flow proposed in the preceding section is particularly promising for high\-quality RTL design generation\. The key strength of this approach is its combination ofmachine intelligence, embodied in frontier AI models, andhuman intelligence, embodied in HLS and domain\-specific compilers\. HLS provides a correct\-by\-construction mechanism for bridging the gap between behavioral specifications expressed in C/C\+\+ or other high\-level languages and the cycle\-accurate implementations required for RTL designs\. Meanwhile, today’s coding agents have demonstrated remarkable capabilities in high\-level programming, leveraging the vast amount of software code represented in their training data, as well as an impressive ability to understand and refine RTL generated by HLS compilers\. The combination of these complementary capabilities makes the AHRR flow particularly powerful in the agentic era\.

It is worth noting that, despite the significant productivity gains offered by HLS, HLS\-based design methodologies have historically seen limited adoption, due in part to two barriers: \(i\) the inertia of existing RTL\-based design practices, which makes designers reluctant to adopt a new methodology, and \(ii\) the difficulty for human designers to read and understand HLS\-generated RTL when cycle\-accurate modifications are required\. AI agents can overcome both barriers\. Unlike human designers, agents can readily explore and adopt HLS\-based methodologies when they produce better results, without being constrained by the inertia of established design practices\. Moreover, agents can effectively understand and further refine the RTL generated by HLS tools when low\-level control is necessary\. We therefore expect agents to substantially accelerate the adoption of HLS and other high\-level design methodologies\. More broadly, our results suggest a promising paradigm for chip design:agents can design better chips by leveraging tools that operate at higher levels of abstraction\.A similar view was also expressed in a recent position paper\([Zhang et al\., 2026b](https://arxiv.org/html/2609.21157#bib.bib5)\)\.

As we completed this study, it is encouraging to see that AI agent \+ HLS design is being adopted by some major industry players, such as the Jalapeño chip designed by OpenAI and announced in August 2026\(jalape~no\)\. No details on the design flow has been released yet, but it is an exciting development\.

###### Acknowledgements\.

This work was partially supported by NSF grants DGE\-2034835, SRC JUMP 2\.0 PRISM Center, Google, Jane Street, and the CDSC industrial partners \(https://cdsc\.ucla\.edu/partners/\)\. The authors thank AMD/Xilinx for HACC equipment donation and HPCfund cluster access\. J\. Cong has a financial interest in AMD and Google\.

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