A Symbolic Neural CPU for Quantization-Simulated Writeback and Interpretable Program Execution

# A Symbolic Neural CPU for Quantization-Simulated Writeback and Interpretable Program Execution
Source: [https://arxiv.org/html/2607.10021](https://arxiv.org/html/2607.10021)
Jose Luis Lima de Jesus SilvaCorresponding author\. Email[mailto:jseluis\.silva@gmail\.com](https://arxiv.org/html/2607.10021v1/mailto:[email protected])Federal University of Bahia, Department of Geophysics, Salvador, BA 40170\-115, BrazilGrupo de Estudos e Aplicação de Inteligência Artificial em Geofísica \(GAIA\), Federal University of Bahia, Salvador, BA 40170\-115, Brazil

###### Abstract

Neural networks can learn algorithmic input\-output mappings, yet learned executors remain difficult to trust because their internal state transitions are usually hidden\. We introduce a trace\-supervised symbolic neural CPU, a factorized learned execution architecture that combines recurrent control, an explicit operation router over a fixed differentiable arithmetic\-logic unit bank, destination\-masked register writeback, complete trajectory supervision and matched fixed\-point replay\. The resulting execution process is auditable through the selected operation, source and destination registers, register trajectory, memory signals and writeback semantics\. On the principal 16\-wide benchmark, the non\-quantized executor reproduces reference execution exactly, while the eight\-bit quantization\-simulated executor preserves the symbolic operation path through programs of 1000 instructions\. Residual numerical drift disappears against a matched fixed\-point replay, identifying a mismatch between continuous and low\-precision reference semantics rather than execution failure\. Architecture comparisons span recurrent, Transformer, temporal\-convolution, temporal graph\-inspired and state\-space controllers\. Ablations show that operation\-gate supervision is necessary for an inspectable execution path, while hidden\-opcode memory\-pressure tasks expose the current limits of delayed state use and temporal binding\. We further extend the interface with ValueMemory, hybrid adaptive leaky integrate\-and\-fire controllers, candidate\-constrained symbolic control trained through behavior cloning and actor\-critic reinforcement learning, and an RV32I base\-integer semantic bridge\. Together, these results establish a trace\-verifiable framework for interpretable, low\-precision and controllable neural execution\.

## 1Introduction

Modern computers are not judged only by their final outputs\. They are auditable transition systems where instructions select operations, operations act on addressable state, and the resulting trajectory can be inspected step by step\. This separation between control, arithmetic, and memory is central to the stored\-program view of computation, where variables can be manipulated by changing the addresses from which values are read and to which values are written\[[53](https://arxiv.org/html/2607.10021#bib.bib1),[58](https://arxiv.org/html/2607.10021#bib.bib2),[14](https://arxiv.org/html/2607.10021#bib.bib10)\]\. Modern neural networks have followed a different route\. They learn continuous input\-output maps from data and are usually evaluated by task\-level accuracy, even when the task itself requires an algorithmic procedure\. The difficulty is therefore not simply whether a neural model can approximate the input\-output behavior of a program, but whether it can expose an execution process sufficiently faithful to be audited as computation\.

This issue has shaped a long line of work at the boundary between learning, memory and reasoning\. Recurrent neural networks \(RNNs\) introduced trainable hidden states for sequence processing, and long short\-term memory \(LSTM\) networks improved the ability of recurrent models to retain information over extended time intervals\[[20](https://arxiv.org/html/2607.10021#bib.bib17),[12](https://arxiv.org/html/2607.10021#bib.bib38),[15](https://arxiv.org/html/2607.10021#bib.bib29)\]\. The sequence\-to\-sequence model, attention mechanisms, and pointer\-like architectures further showed that neural networks can learn flexible forms of alignment, retrieval, and structured sequential manipulation\[[50](https://arxiv.org/html/2607.10021#bib.bib39),[2](https://arxiv.org/html/2607.10021#bib.bib40),[57](https://arxiv.org/html/2607.10021#bib.bib41)\]\. These new developments made neural systems increasingly capable of acting over temporally extended inputs, but the stored information generally remained embedded in hidden activations or learned parameters rather than represented as an explicitly inspectable machine state\.

Memory\-augmented neural networks made this computer analogy more direct\. Neural Turing machines \(NTMs\) and differentiable neural computers \(DNCs\) coupled a neural controller to an external memory matrix that can be read from and written to through differentiable addressing\[[13](https://arxiv.org/html/2607.10021#bib.bib9),[14](https://arxiv.org/html/2607.10021#bib.bib10)\]\. The DNC added content lookup, temporal linkage, and dynamic allocation, enabling learned systems to answer synthetic reasoning questions, traverse graphs, infer shortest paths, and carry out planning\-like block manipulation\[[14](https://arxiv.org/html/2607.10021#bib.bib10)\]\. Related memory\-network and end\-to\-end memory\-network architectures also demonstrated the value of separating a learned controller from an addressable store for reasoning over facts and sequences\[[59](https://arxiv.org/html/2607.10021#bib.bib42),[49](https://arxiv.org/html/2607.10021#bib.bib43)\]\. More recently, Transformer attention has been interpreted as a restricted, stateless form of DNC\-like memory access, in which keys and values form a write\-once memory and multi\-head attention implements parallel content\-based reads\[[55](https://arxiv.org/html/2607.10021#bib.bib11),[52](https://arxiv.org/html/2607.10021#bib.bib30)\]\. These results establish external or attention\-mediated memory as a central mechanism in neural computation\. They do not, however, provide a register\-level audit of which symbolic operation was selected, which state variable was updated, and whether the intermediate execution path matches a reference machine\.

Neural algorithmic reasoning addresses a complementary question: whether neural networks can imitate the execution of classical algorithms\. The CLRS Algorithmic Reasoning Benchmark, a suite of algorithmic tasks inspired by the textbook tradition of Cormen, Leiserson, Rivest, and Stein, evaluates models on sorting, searching, graph, string, and dynamic\-programming problems, often using supervision over intermediate algorithm states rather than final answers alone\[[8](https://arxiv.org/html/2607.10021#bib.bib44),[56](https://arxiv.org/html/2607.10021#bib.bib45),[32](https://arxiv.org/html/2607.10021#bib.bib31)\]\. Open\-book neural algorithmic reasoning extends this setting by allowing a model to consult training instances during inference, turning examples into an auxiliary memory for reasoning\[[32](https://arxiv.org/html/2607.10021#bib.bib31)\]\. Recent work on Transformer\-NAR hybrids, tropical attention, primal\-dual neural reasoners, looped Transformer simulations, and knapsack\-style intermediate supervision further shows that architectural bias and intermediate\-state supervision can improve neural reasoning on graph, combinatorial, and dynamic\-programming tasks\[[5](https://arxiv.org/html/2607.10021#bib.bib47),[18](https://arxiv.org/html/2607.10021#bib.bib48),[19](https://arxiv.org/html/2607.10021#bib.bib49),[33](https://arxiv.org/html/2607.10021#bib.bib50),[42](https://arxiv.org/html/2607.10021#bib.bib51)\]\. This literature is similar to trace\-supervised execution because it treats intermediate computation as an object of learning\. Yet its intermediate states are usually graph\- or task\-specific algorithm states\. They are not machine states composed of registers, destination masks, operation gates, and low\-precision writebacks\.

A second related thread studies neural programs and neurosymbolic execution\. In neural\-program learning, a neural model is composed of a symbolic program, logic program, or black\-box application programming interface \(API\), and learning requires propagating supervision through, around, or across that symbolic component\[[48](https://arxiv.org/html/2607.10021#bib.bib32)\]\. Such methods are powerful because the program can enforce exact structure while the neural component handles perception, uncertainty, or incomplete inputs\. The setting studied here is different\. Rather than attaching a neural model to an external executor, the aim is to learn the executor itself while keeping it auditable\. In this setting, the operation distribution, hard operation choice, register trajectory, and low\-precision arithmetic are not hidden implementation details because they are the objects being evaluated\. Related work on code simulation and differentiable program synthesis similarly treats stepwise execution as a demanding reasoning problem, but typically evaluates code\-like behavior, latent program search, or learned symbolic primitives rather than register\-level operation paths with matched fixed\-point replay\[[30](https://arxiv.org/html/2607.10021#bib.bib52),[35](https://arxiv.org/html/2607.10021#bib.bib53)\]\.

The same demand for state\-level evaluation appears at larger scales in memory\-augmented agents based on large language models \(LLMs\)\. Persistent LLM agents increasingly rely on external memory banks, but recent work shows that memory is not a passive store\. Therefore, the construction, retrieval, and utilization form a coupled cycle, and downstream errors should feed back into memory repair\[[34](https://arxiv.org/html/2607.10021#bib.bib33)\]\. The continual learning studies of memory\-augmented agents similarly show that external memory does not remove interference\. It actually shifts the bottleneck from parameter overwriting to memory representation, retrieval, and context competition\[[21](https://arxiv.org/html/2607.10021#bib.bib34)\]\. These observations support a general principle that memory\-augmented computation should not be evaluated solely by the correctness of the final response\. This means we should also consider whether the stored, retrieved, and updated state supports the intended computation\. We study this principle at the level of controlled register\-machine traces, where the relevant state is a register file and optional external memory rather than a conversational memory bank\.

The device\-facing execution imposes an additional constraint\. Quantization\-aware training \(QAT\), mixed\-precision search, and hardware\-aware compression show that neural models often need to be evaluated under explicit budgets for memory, bit\-width, latency, and computational cost before deployment on constrained hardware\[[24](https://arxiv.org/html/2607.10021#bib.bib6),[28](https://arxiv.org/html/2607.10021#bib.bib7),[54](https://arxiv.org/html/2607.10021#bib.bib35)\]\. In addition, energy\-aware inference studies similarly emphasized that accuracy alone is insufficient when computation is constrained by power and latency\[[23](https://arxiv.org/html/2607.10021#bib.bib36)\]\. The analog in\-memory training goes further by investigating which learning algorithms remain viable when computation is mapped onto non\-ideal memory devices\[[43](https://arxiv.org/html/2607.10021#bib.bib37)\]\. Therefore, these hardware\-oriented works motivate low\-precision and cost\-aware evaluation, but they usually optimize neural inference workloads\. By contrast, they do not test whether a learned symbolic executor preserves a stepwise machine trace when arithmetic is projected onto a fixed\-point grid with quantization\-simulated writeback, rather than with full integer\-only inference\. Recent work on full\-integer deployment and rescaling\-aware training makes this distinction especially important, because low\-precision arithmetic can introduce deployment costs and behaviors that are not visible in floating\-point evaluation alone\[[38](https://arxiv.org/html/2607.10021#bib.bib54)\]\.

The hardware context is also changing, as evidenced by neuromorphic many\-core processors such as Loihi, which demonstrated programmable, event\-driven substrates with on\-chip learning, while deterministic neuromorphic systems such as NeuroScale use local, event\-driven synchronization to preserve reproducible spike timing without global barriers\[[10](https://arxiv.org/html/2607.10021#bib.bib21),[31](https://arxiv.org/html/2607.10021#bib.bib55)\]\. At a more conceptual level, recent work on neural computers frames learned runtimes as an emerging machine form in which computation, memory, and I/O are unified in model state, while emphasizing that stable execution and symbolic control remain open problems\[[61](https://arxiv.org/html/2607.10021#bib.bib56)\]\. At the processor interface,RISC\-V\-based SNN accelerators such as FeNN show that programmable instruction\-set\-compatible platforms are being adapted for spiking neural workloads\[[1](https://arxiv.org/html/2607.10021#bib.bib57)\]\. Together with analog in\-memory training and full\-integer deployment work, these systems point toward real neural\-computing modules in which low\-precision arithmetic, memory state and programmable control will need to be verified at the level of state transitions rather than only benchmark accuracy\[[43](https://arxiv.org/html/2607.10021#bib.bib37),[38](https://arxiv.org/html/2607.10021#bib.bib54)\]\. However, they do not supply an audit trail for learned symbolic execution\.

This gap motivates the central direction of the present work\. If learned executors are to become controllers, co\-processors or device\-facing runtimes, their operation choices, register writes, memory effects and low\-precision replay semantics must be visible before hardware deployment\. We therefore develop an inspectable execution interface, where a simulation\-stage symbolic neural executor whose operation gate, destination mask, register trajectory and matched fixed\-point replay can be compared with a reference machine\. The goal is to make future systems inspectable at the transition level\. Therefore, the current model is not presented as a physical processor implementation\. The primary experiments investigated symbolic execution and matched fixed\-point replay under controlled conditions\. As a standardized\-ISA bridge, we further tested whether the same design principles can be attached to an RV32I base\-integer semantic substrate\. This RV32I experiment was a semantic bridge and learned\-control diagnostic, not officialRISC\-Vcompliance, privileged execution, ABI/runtime support or hardware execution\.

What remains missing is an audit layer between neural algorithmic behaviour and deployable execution, where a controlled setting in which a learned system must expose the selected operation, the updated register, the complete intermediate trajectory and the effect of low\-precision arithmetic\. We address this gap by developing an inspectable execution interface\. Therefore, we instantiated the interface with a trace\-supervised symbolic neural executor\. The model receives register\-machine instructions and learns to update a normalized register state through a bank of named continuous arithmetic and logic operations\. Its transition is trained as a differentiable approximation to a symbolic state machine,

𝒯:𝒮×ℐ→𝒮,\\mathcal\{T\}:\\mathcal\{S\}\\times\\mathcal\{I\}\\rightarrow\\mathcal\{S\},\(1\)but it is evaluated at the level at which a computer would be audited, considering a final state, full register trace, operation\-gate agreement, deterministic hard execution, matched fixed\-point replay behaviour, and dimensionless proxy energy and delay\.

We have constructed this setting by generating controlled instruction sequences over continuous register vectors in\[0,1\]\[0,1\]\(profile widths88,1616or3232\) with exact reference traces, including the initial register file, the per\-step register trajectory, the final state, operation labels, destination masks, and proxy energy and delay traces\. A neural executor was then trained to imitate the reference transition using a factorized architecture\. Therefore, we have an architecture with an instruction encoder, a recurrent controller, an optional differentiable memory read/write pathway, a named operation router, a continuous arithmetic\-logic unit \(ALU\) bank, and a masked destination\-register writeback\. In our case, the ALU bank denotes the set of differentiable arithmetic and logical operators that the model selects at each instruction step\. During training, the application of stochastic operation selection through the Gumbel\-Softmax relaxation provides a differentiable path, while evaluation uses deterministic hard operation choices to test whether the learned executor follows an inspectable symbolic path rather than only matching the endpoint\[[25](https://arxiv.org/html/2607.10021#bib.bib46),[36](https://arxiv.org/html/2607.10021#bib.bib16)\]\.

This controlled register\-machine setting exposes the stepwise machine state that is usually hidden in neural sequence prediction\. Each sample contains the instruction stream, initial register file, operation labels, destination masks, complete register trajectory, and final state\. The executor is trained and evaluated against these objects rather than against a scalar endpoint alone\. A single experiment can therefore investigate separate questions of whether the model chooses the correct named operation, preserves non\-destination registers, follows the reference trajectory, remains stable under deterministic hard execution, and agrees with a matched low\-precision replay\.

In this study, we have imposed three constraints on the learned executor: \(i\) supervision that includes the complete reference trajectory, therefore the success requires trace faithfulness rather than endpoint imitation alone, \(ii\) operation selection which is exposed through named gates and evaluated in both soft Gumbel\-Softmax training and hard deterministic execution, so the learned path can be inspected rather than hidden inside a dense recurrent state, and \(iii\) quantization\-simulated writeback which is scored against both a continuous reference and a matched fixed\-point replay, separating low\-precision reference drift from execution error under the model’s own writeback semantics\. On the principal 16\-wide register\-machine profile, these constraints enabled the evaluation of matched replay, length extrapolation, simulated input perturbations, calibration, equivalent lower\-cost programs, architecture ablations, hidden\-opcode memory pressure, spiking\-controller variants, candidate\-constrained closed\-loop control, and an RV32I base\-integer semantic bridge\. The result is a controlled register\-machine substrate, and not a general differentiable neural computer, neural algorithmic reasoner, or program synthesizer, for testing whether learned execution preserves the operation path, intermediate machine trajectory, and low\-precision reference semantics behind a final answer\. The scope limitations are consolidated in the Discussion\.

## 2Methods

### 2\.1Execution interface

All experiments use the same controlled register\-machine interface, shown schematically in[Figure˜1](https://arxiv.org/html/2607.10021#S3.F1)\. This interface follows the register\-machine and small\-step operational view of computation, in which execution is represented as a sequence of state transitions over an explicit machine state\[[46](https://arxiv.org/html/2607.10021#bib.bib58),[41](https://arxiv.org/html/2607.10021#bib.bib59)\]\. The figure gives the architectural view of the executor, and shows the state, instruction, operation, writeback and replay objects used throughout the experiments\.

A program has lengthTTand is executed over discrete stepst∈\{1,…,T\}t\\in\\\{1,\\ldots,T\\\}\. The machine state at stepttis a register file

rt∈\[0,1\]R×W,r\_\{t\}\\in\[0,1\]^\{R\\times W\},\(2\)whereRRis the number of registers andWWis the number of scalar lanes in each register\. The vectorrt,j∈\[0,1\]Wr\_\{t,j\}\\in\[0,1\]^\{W\}denotes registerjjat steptt\. The widthWWis a continuous register\-vector width\. It is not an integer bit width and should not be read as a 16\-bit or 32\-bit instruction\-set architecture\.

Each instruction is a tuple

ξt=\(ot,it,jt,dt\),\\xi\_\{t\}=\(o\_\{t\},i\_\{t\},j\_\{t\},d\_\{t\}\),\(3\)whereot∈𝒪o\_\{t\}\\in\\mathcal\{O\}is the named operation,iti\_\{t\}andjtj\_\{t\}are the two source\-register indices, anddtd\_\{t\}is the destination\-register index\. The source and destination indices satisfy

it,jt,dt∈\{0,…,R−1\}\.i\_\{t\},j\_\{t\},d\_\{t\}\\in\\\{0,\\ldots,R\-1\\\}\.The main operation set is

𝒪=\{AND,OR,XOR,ADD,SUB,SHL,SHR,MUL\}\.\\mathcal\{O\}=\\\{\\mathrm\{AND\},\\mathrm\{OR\},\\mathrm\{XOR\},\\mathrm\{ADD\},\\mathrm\{SUB\},\\mathrm\{SHL\},\\mathrm\{SHR\},\\mathrm\{MUL\}\\\}\.\(4\)The operation mnemonics denote logical AND, logical OR, exclusive OR \(XOR\), addition \(ADD\), subtraction \(SUB\), shift left \(SHL\), shift right \(SHR\) and multiplication \(MUL\)\. These names label fixed continuous operations inspired by Central Processing Unit \(CPU\) instruction categories\[[40](https://arxiv.org/html/2607.10021#bib.bib60)\]\. They do not claim bit\-accurate integer arithmetic in the present implementation\.

The reference interpreter reads the two source operands

ut=rt−1,it,vt=rt−1,jt,u\_\{t\}=r\_\{t\-1,i\_\{t\}\},\\qquad v\_\{t\}=r\_\{t\-1,j\_\{t\}\},\(5\)applies the operationAotA\_\{o\_\{t\}\}from the fixed continuous arithmetic logic unit \(ALU\) bank, and writes the result only to the destination register\. For each registerqq, the reference transition is

rt,q=\{Aot​\(ut,vt\),q=dt,rt−1,q,q≠dt\.r\_\{t,q\}=\\begin\{cases\}A\_\{o\_\{t\}\}\(u\_\{t\},v\_\{t\}\),&q=d\_\{t\},\\\\ r\_\{t\-1,q\},&q\\neq d\_\{t\}\.\\end\{cases\}\(6\)This write rule is the locality constraint of the interface\. One instruction may change the destination register, while all non\-destination registers are preserved\.

The instruction vector used by the learned executor is

xt=\[onehot​\(ot\),itDR,jtDR,dtDR\],DR=max⁡\(1,R−1\)\.x\_\{t\}=\\left\[\\mathrm\{onehot\}\(o\_\{t\}\),\\frac\{i\_\{t\}\}\{D\_\{R\}\},\\frac\{j\_\{t\}\}\{D\_\{R\}\},\\frac\{d\_\{t\}\}\{D\_\{R\}\}\\right\],\\qquad D\_\{R\}=\\max\(1,R\-1\)\.\(7\)Here,onehot​\(ot\)\\mathrm\{onehot\}\(o\_\{t\}\)is the one\-hot encoding of the operation label, andDRD\_\{R\}is the guarded denominator used to normalize register indices\. For the main operation set, this gives an\|𝒪\|\+3=11\|\\mathcal\{O\}\|\+3=11dimensional instruction encoding\. The executor receivesxtx\_\{t\}, the previous predicted register filer^t−1\\hat\{r\}\_\{t\-1\}and, when enabled, a differentiable memory read vector\. It then predicts operation logits

ℓt=frouter​\(\[r^t−1,it,r^t−1,jt,at,onehot​\(ot\)\]\),ℓt∈ℝ\|𝒪\|,\\ell\_\{t\}=f\_\{\\mathrm\{router\}\}\\left\(\[\\hat\{r\}\_\{t\-1,i\_\{t\}\},\\hat\{r\}\_\{t\-1,j\_\{t\}\},a\_\{t\},\\mathrm\{onehot\}\(o\_\{t\}\)\]\\right\),\\qquad\\ell\_\{t\}\\in\\mathbb\{R\}^\{\|\\mathcal\{O\}\|\},\(8\)whereata\_\{t\}is an auxiliary controller projection andfrouterf\_\{\\mathrm\{router\}\}is the operation router\. The corresponding soft operation distribution is

πt=softmax​\(ℓt/τ\),\\pi\_\{t\}=\\mathrm\{softmax\}\(\\ell\_\{t\}/\\tau\),\(9\)whereτ\>0\\tau\>0is the gate temperature\. Deterministic evaluation uses the hard operation

o^t=arg⁡maxk∈𝒪⁡ℓt,k\.\\hat\{o\}\_\{t\}=\\arg\\max\_\{k\\in\\mathcal\{O\}\}\\ell\_\{t,k\}\.\(10\)The indexkkranges over the named operations in𝒪\\mathcal\{O\}\. This factorized pathway is related to earlier neural execution and neural programming models, including recurrent program execution, differentiable operation selection, supervised neural interpreters, neural random\-access memory and neural algorithm learners\[[60](https://arxiv.org/html/2607.10021#bib.bib61),[39](https://arxiv.org/html/2607.10021#bib.bib62),[44](https://arxiv.org/html/2607.10021#bib.bib63),[29](https://arxiv.org/html/2607.10021#bib.bib64),[26](https://arxiv.org/html/2607.10021#bib.bib65)\]\. The present interface differs by making the operation gate, destination mask, register trajectory and matched fixed\-point replay explicit evaluation objects\.

For each operationk∈𝒪k\\in\\mathcal\{O\}, the executor computes a candidate ALU output

yt,k=Ak​\(r^t−1,it,r^t−1,jt\)\.y\_\{t,k\}=A\_\{k\}\(\\hat\{r\}\_\{t\-1,i\_\{t\}\},\\hat\{r\}\_\{t\-1,j\_\{t\}\}\)\.\(11\)Soft execution uses the mixture

y^tsoft=∑k∈𝒪πt,k​yt,k,\\hat\{y\}\_\{t\}^\{\\mathrm\{soft\}\}=\\sum\_\{k\\in\\mathcal\{O\}\}\\pi\_\{t,k\}y\_\{t,k\},\(12\)whereas hard deterministic execution uses

y^thard=yt,o^t\.\\hat\{y\}\_\{t\}^\{\\mathrm\{hard\}\}=y\_\{t,\\hat\{o\}\_\{t\}\}\.\(13\)The selected writeback value is denoted byy^t\\hat\{y\}\_\{t\}\. The predicted register file is updated by the destination mask

r^t,q=\{y^t,q=dt,r^t−1,q,q≠dt\.\\hat\{r\}\_\{t,q\}=\\begin\{cases\}\\hat\{y\}\_\{t\},&q=d\_\{t\},\\\\ \\hat\{r\}\_\{t\-1,q\},&q\\neq d\_\{t\}\.\\end\{cases\}\(14\)If a padding mask marks stepttas invalid, the implementation leaves the predicted state unchanged and excludes the step from masked trace and gate losses\. The padding mask is the binary batching mask that separates real program steps from padded positions\.

The interface is both a model pathway and a measurement surface\. At each valid step it exposes the encoded instruction, source operands, destination register, operation logits, operation probabilities, hard operation choice, predicted writeback value, predicted register state and reference target\. Evaluation compares these objects with the reference machine using final\-state error, full\-trace error, gate agreement, deterministic hard execution and matched fixed\-point replay\. Endpoint accuracy alone is not used as the definition of successful execution\.

In the eight\-bit quantization\-simulated writeback setting \(QAT8\), the selected writeback value is projected onto a uniform eight\-bit fixed\-point grid before it is written to the destination register\. This simulated writeback projection is related to the broader literature on low\-precision and quantized neural computation\[[9](https://arxiv.org/html/2607.10021#bib.bib67),[22](https://arxiv.org/html/2607.10021#bib.bib68),[11](https://arxiv.org/html/2607.10021#bib.bib69)\], while the matched replay below defines the specific reference semantics used in this study\. For a tensorx∈\[0,1\]x\\in\[0,1\]and bit depthBB, the projection is

QB​\(x\)=clip​\(round​\(x​\(2B−1\)\),0,2B−1\)2B−1\.Q\_\{B\}\(x\)=\\frac\{\\mathrm\{clip\}\\left\(\\mathrm\{round\}\\left\(x\(2^\{B\}\-1\)\\right\),0,2^\{B\}\-1\\right\)\}\{2^\{B\}\-1\}\.\(15\)Here,round\\mathrm\{round\}denotes elementwise nearest\-grid rounding, andclip\\mathrm\{clip\}limits each component to the interval\[0,2B−1\]\[0,2^\{B\}\-1\]\. QAT8 usesB=8B=8\. The quantized model writeback is thereforeQ8​\(y^t\)Q\_\{8\}\(\\hat\{y\}\_\{t\}\)in the standard QAT8 executor\.

The matched fixed\-point replay applies the same writeback projection to the reference interpreter\. Its transition is

rt,q\(B\)=\{QB​\(Aot​\(rt−1,it\(B\),rt−1,jt\(B\)\)\),q=dt,rt−1,q\(B\),q≠dt\.r^\{\(B\)\}\_\{t,q\}=\\begin\{cases\}Q\_\{B\}\\\!\\left\(A\_\{o\_\{t\}\}\(r^\{\(B\)\}\_\{t\-1,i\_\{t\}\},r^\{\(B\)\}\_\{t\-1,j\_\{t\}\}\)\\right\),&q=d\_\{t\},\\\\ r^\{\(B\)\}\_\{t\-1,q\},&q\\neq d\_\{t\}\.\\end\{cases\}\(16\)The statert\(B\)r^\{\(B\)\}\_\{t\}denotes the reference trajectory replayed at bit depthBB\. This replay is an external scoring reference computed after model execution\. It does not consult the model outputs, it is not a runtime fallback, and it is not full integer\-only inference\. It tests whether the learned QAT8 executor agrees with the reference machine under the same writeback precision\.

Optional memory variants keep the same interface\. The gated recurrent unit with Neural Turing Machine memory \(GRU\-NTM\) executor uses a slot\-addressed memory read vector\. In addition, the ValueMemory variant uses a value\-addressed memory pathway for hidden\-opcode memory\-pressure tasks\. At most one memory variant is active in a trained instance\. The exposed inspection objects remain the same, since they are the operation path, destination writeback, register trajectory and replay semantics\.

### 2\.2Dataset generation and training

The shared execution interface in[section˜3\.1](https://arxiv.org/html/2607.10021#S3.SS1)is generated from synthetic register\-machine programs\. Each program is sampled by choosing a task family, length, opcode sequence, source\-register indices and destination\-register indices under a fixed CPU profile\. The principal 16\-wide profile uses training lengths 10\-60\. The original benchmark bundle evaluates held\-out lengths 30, 60, 100 and 200, and the long\-horizon analysis evaluates the trained instances on the extended gridL∈\{20,30,40,60,80,100,140,200,260,320,400,500,600,700,800,900,1000\}L\\in\\\{20,30,40,60,80,100,140,200,260,320,400,500,600,700,800,900,1000\\\}\. Additionally, the 32\-wide extrapolation analyses use the same generator on wider continuous register vectors\. Each sample stores instruction features, initial registers, final reference registers, the reference register trace, operation labels, proxy energy and delay traces, and a valid\-step mask\. Energy\-choice datasets add alternate and minimum\-energy traces, alternate instruction streams, total proxy costs and minimum\-energy path labels\.

The main medium 16\-wide experiments use 3000 training programs, 500 validation programs, batch size 16, learning rate10−310^\{\-3\}, 30 epochs, hidden size 64, 32 memory slots and memory dimension of 32\. Gumbel gate training usesτ\\tauannealed from 2\.0 to 0\.5, and the deterministic evaluation uses hard argmax gates\. The standardQAT8runs use 8\-bit quantization simulation of the selectedALUoutput before destination writeback, optionally with a 5\-epoch warmup\. The ValueMemory\-QAT8variants quantize theALUoutput before the later value\-memory blend rather than re\-quantizing the final blended destination value\.

### 2\.3Metrics

Letmn,t∈\{0,1\}m\_\{n,t\}\\in\\\{0,1\\\}be the padding mask and let

Nm=∑n,tmn,tN\_\{m\}=\\sum\_\{n,t\}m\_\{n,t\}\(17\)be the number of active program steps in an evaluated batch or pooled benchmark family\. For each sequencenn,TnT\_\{n\}denotes its last active timestep\. Final MAE is

MAEF=1NB​R​W​∑n=1NB∑j=1R∑k=1W\|r^Tn,j,k\(n\)−rTn,j,k\(n\)\|\.\\mathrm\{MAE\}\_\{F\}=\\frac\{1\}\{N\_\{B\}RW\}\\sum\_\{n=1\}^\{N\_\{B\}\}\\sum\_\{j=1\}^\{R\}\\sum\_\{k=1\}^\{W\}\|\\hat\{r\}\_\{T\_\{n\},j,k\}^\{\(n\)\}\-r\_\{T\_\{n\},j,k\}^\{\(n\)\}\|\.\(18\)Trace MAE is

MAET=1Nm​R​W​∑n,tmn,t​∑j=1R∑k=1W\|r^t,j,k\(n\)−rt,j,k\(n\)\|\.\\mathrm\{MAE\}\_\{T\}=\\frac\{1\}\{N\_\{m\}RW\}\\sum\_\{n,t\}m\_\{n,t\}\\sum\_\{j=1\}^\{R\}\\sum\_\{k=1\}^\{W\}\|\\hat\{r\}\_\{t,j,k\}^\{\(n\)\}\-r\_\{t,j,k\}^\{\(n\)\}\|\.\(19\)Gate agreement is

AG=1Nm​∑n,tmn,t​𝟏​\[arg​maxo∈𝒪​πt,o\(n\)=ot\(n\)\]\.A\_\{G\}=\\frac\{1\}\{N\_\{m\}\}\\sum\_\{n,t\}m\_\{n,t\}\\mathbf\{1\}\[\\mathrm\{arg\\,max\}\_\{o\\in\\mathcal\{O\}\}\\pi\_\{t,o\}^\{\(n\)\}=o\_\{t\}^\{\(n\)\}\]\.\(20\)Tolerance faithfulness is

Fϵ=1NB​∑n=1NB𝟏​\[‖r^Tn\(n\)−rTn\(n\)‖∞≤ϵ\]\.F\_\{\\epsilon\}=\\frac\{1\}\{N\_\{B\}\}\\sum\_\{n=1\}^\{N\_\{B\}\}\\mathbf\{1\}\\left\[\\\|\\hat\{r\}\_\{T\_\{n\}\}^\{\(n\)\}\-r\_\{T\_\{n\}\}^\{\(n\)\}\\\|\_\{\\infty\}\\leq\\epsilon\\right\]\.\(21\)Exact low\-precision faithfulness is reported as equality after both predicted and reference register components are projected onto the same scalar quantization grid\. The grid resolution is tied to the register\-vector profile widthWW\. The diagnostic is scalar\-component agreement on that grid, not equality of packed integer machine words\. Calibration is computed after flattening active gate predictions\. Expected calibration error is

ECE=∑m=1M\|Cm\|Nm​\|acc​\(Cm\)−conf​\(Cm\)\|,\\mathrm\{ECE\}=\\sum\_\{m=1\}^\{M\}\\frac\{\|C\_\{m\}\|\}\{N\_\{m\}\}\\left\|\\mathrm\{acc\}\(C\_\{m\}\)\-\\mathrm\{conf\}\(C\_\{m\}\)\\right\|,\(22\)whereCmC\_\{m\}is confidence binmmover active timesteps\. The Brier score is

Brier=1Nm​∑n,tmn,t​∑o∈𝒪\(πt,o\(n\)−𝟏​\[o=ot\(n\)\]\)2\.\\mathrm\{Brier\}=\\frac\{1\}\{N\_\{m\}\}\\sum\_\{n,t\}m\_\{n,t\}\\sum\_\{o\\in\\mathcal\{O\}\}\\left\(\\pi\_\{t,o\}^\{\(n\)\}\-\\mathbf\{1\}\[o=o\_\{t\}^\{\(n\)\}\]\\right\)^\{2\}\.\(23\)HereNm=∑n,tmn,tN\_\{m\}=\\sum\_\{n,t\}m\_\{n,t\}is the number of active instruction steps\. The implemented score sums squared error over the operation dimension rather than dividing by\|𝒪\|\|\\mathcal\{O\}\|\. In benchmark reporting, calibration is interpreted for*soft\-mode*probabilities\. Deterministic hard execution is summarized by argmax gate agreement, and the one\-hot hard gates are not treated as evidence of probability calibration\.

### 2\.4Statistical aggregation

For benchmark tables, each row aggregates over all examples and batches specified by the corresponding benchmark configuration\. Where multi\-seed sweeps are available, results are summarized as mean and standard deviation:

x¯=1S​∑s=1Sxs,σx=1S−1​∑s=1S\(xs−x¯\)2\.\\bar\{x\}=\\frac\{1\}\{S\}\\sum\_\{s=1\}^\{S\}x\_\{s\},\\qquad\\sigma\_\{x\}=\\sqrt\{\\frac\{1\}\{S\-1\}\\sum\_\{s=1\}^\{S\}\(x\_\{s\}\-\\bar\{x\}\)^\{2\}\}\.\(24\)For paired comparisons, such as baseline versus candidate control under the same task set, the paired difference is

Δs=xscandidate−xsbaseline\.\\Delta\_\{s\}=x\_\{s\}^\{\\mathrm\{candidate\}\}\-x\_\{s\}^\{\\mathrm\{baseline\}\}\.\(25\)When the sample count is sufficient, a pairedttstatistic is

t=Δ¯sΔ/S,t=\\frac\{\\bar\{\\Delta\}\}\{s\_\{\\Delta\}/\\sqrt\{S\}\},\(26\)wheresΔs\_\{\\Delta\}is the standard deviation of paired differences\. These experiments emphasize effect sizes, task\-level breakdowns and confidence intervals over formal significance claims when long\-horizon control evaluations have limited seed counts\. The figures therefore separate stable benchmark effects from regimes where independent replication remains limited and where additional seeds would be required for stronger inferential claims\.

For the symbolic\-execution benchmark of[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2), distribution\-free uncertainty and significance are computed from the existing benchmark outputs\. Each metric is summarized over the pooled per\-length, per\-batch evaluation samples of a family, and95%95\\%confidence intervals are obtained by a percentile bootstrap of the mean \(10,00010\{,\}000resamples, fixed seed\)\. Paired metric comparisons within a family \(e\.g\. trace versus finalMAE\\mathrm\{MAE\}\) use the Wilcoxon signed\-rank test, and two\-regime comparisons \(e\.g\. the 32\-wide extrapolation profile atL≤320L\\leq 320versusL≥600L\\geq 600\) use the Mann–WhitneyUUtest\. These statistics are quoted inline where the corresponding claims are made\.

### 2\.5Diagnostic protocols and extensions

This subsection defines the diagnostic protocols used outside the primary visible\-opcode execution benchmark\. These protocols keep the same execution interface when possible, but change the evaluation setting\. They include the RV32I semantic bridge, architecture baselines, hidden\-opcode memory pressure, spiking\-controller variants and rollout\-level diagnostic panels\.

RV32I semantic bridge\.The RV32I semantic bridge used in[fig\.˜7](https://arxiv.org/html/2607.10021#S3.F7)represents each instruction as an unsigned 32\-bit word\. The decoder extracts opcode, rd, rs1, rs2, funct3, funct7 and I/S/B/U/J immediate fields using RV32I bit positions and sign extension\. Here, rd is the destination register and rs1 and rs2 are source\-register fields\. Legal base\-integer encodings are mapped to instruction names and instruction families\. Unsupported encodings enter an illegal\-instruction trap state\.

The machine state is represented by a 32\-entry unsigned 32\-bit register file, a byte\-addressed memory array, an integer program counter and a string\-valued trap field\. Register x0 is reset to zero after every step, enforcing architectural zero\-register invariance\. The step function checks for a pre\-existing trap and program\-counter alignment before applying instruction semantics\. LUI and AUIPC write upper\-immediate values\. JAL and JALR write the link register and update the program counter, with JALR clearing the low target bit\. Branches compare signed or unsigned operands according to funct3 and update the program counter when taken\. Loads and stores compute effective addresses from rs1 plus the relevant immediate and apply width\-specific alignment and bounds checks\. OP\-IMM and OP instructions call symbolicALUhelpers for addition, subtraction, comparisons, bitwise operations and shifts\. FENCE is treated as a single\-hart no\-op\. ECALL and EBREAK enter explicit trap states\.

RV32I audit and harness\.The deterministic audit enumerates the implemented RV32I base\-integer inventory and combines direct unit tests with randomized property tests\. Direct tests cover x0 invariance, arithmetic and comparisons, load and store widths, branch targets, JAL and JALR link behaviour, LUI and AUIPC, alignment traps, FENCE, ECALL, EBREAK and illegal\-instruction handling\. Randomized properties test immediate sign extension, signed and unsigned comparisons, branch target selection, load and store round trips, sign extension, alignment traps, memory out\-of\-bounds traps and random program\-level invariants\. The full audit used 8,192 generated programs, 16,384 property cases, lengths 16 to 384, a maximum of 512 execution steps and 4,096 bytes of memory\.

The architectural harness runs raw instruction\-word programs through the deterministic bridge and records a signature\-memory region\. It initializes registers and memory deterministically, supports external machine\-code programs and structured test specifications, and can check expected signature prefixes, trap states and register values\. The harness is designed to match the shape of future architectural compliance testing\.

RV32I learned\-control diagnostic\.The learned\-control experiment separates deterministic RV32I replay from learned control prediction\. Instruction\-level models predict operation name and register fields from either raw instruction bits or decoded bitfield features\. Semantic\-control models predict program\-counter mode, memory mode and writeback mode from instruction and state features\. Program\-counter modes are fall\-through, branch taken, branch not taken, jump, jump\-register and trap\. Memory modes are none, load, store and trap\. Writeback modes are none, write rd, x0 suppressed and trap\.

The rescue model reported in[fig\.˜7](https://arxiv.org/html/2607.10021#S3.F7)concatenates decoded bitfield features with symbolic RV32I predicates\. These include one\-hot instruction name and family, normalized immediate values, equality and signed or unsigned comparison predicates, branch\-taken predicates, branch, JAL and JALR target\-alignment predicates, load and store effective\-address predicates, memory\-width indicators, signed\-load indicators, out\-of\-bounds and misalignment indicators, program\-counter alignment, illegal and trap indicators and rd==0\. The model is a compact multilayer perceptron with separate heads for program\-counter mode, memory mode and writeback mode\. The cross\-entropy losses are applied to each control head, with optional class weighting for rare modes\.

For the multi\-seed diagnostic in[fig\.˜7](https://arxiv.org/html/2607.10021#S3.F7), the symbolic\-predicate semantic\-control model was repeated with seeds 42, 43 and 44\. Each run used 500,000 training samples, 100,000 validation samples, 4,096 evaluation programs, 96 epochs, batch size 1,024, hidden width 320, learning rate10−310^\{\-3\}, program lengths 16 to 256, a maximum of 384 execution steps, 4,096 bytes of memory and semantic class\-weight power 0\.5\. Program\-level summaries report mean and s\.d\. across seeds\. Step agreement is the joint semantic\-control accuracy over program\-counter, memory and writeback heads\. Program\-exact sequence accuracy requires every program\-counter, memory and writeback decision in the evaluated sequence to be correct\. Mode\-level summaries stratify predictions by target head and semantic mode\. The targeted rescue panel reports the prespecified weak\-mode metrics, which means the held\-out program exact, branch and memory challenge program exact, length\-extrapolation exact, length\-extrapolation step agreement, trap, jump\-register, load and store\.

Architecture\-backed RV32I executor\.The architecture\-backed RV32I executor is a separate derivative of the symbolic neural CPU design principles rather than the main trained executor\. RV32I decode and predicate features are supplied to a learned micro\-operation lowerer, passed through aGRUcontroller, read through a scalar value\-memory lane and routed through a gatedALUoperation bank\. Output heads predict program\-counter mode, memory mode, writeback mode, auxiliaryALUoperation, register indices andALUvalue\. This executor mirrors the article’s core ingredients, namely recurrent control, value\-addressed memory and learnedALUrouting, while adapting them to RV32I teacher traces generated by the deterministic bridge\.

Architecture baselines\.All comparison architecture variants use the same dataset and benchmark protocol\. They are not parameter\-matched or memory\-interface\-matched\. Some models have different parameter counts due to controller architecture\. The comparison is therefore used as an architectural diagnostic, with the no\-gate\-loss ablation providing the capacity\-preserving test of gate supervision\. The scratchpad baseline predicts traces without explicit gates\. Gate metrics are therefore not computed for that baseline rather than imputed\. The no\-gate\-loss model uses the main architecture withλG=0\\lambda\_\{G\}=0, testing whether gate supervision matters independently of capacity\.

Memory\-pressure benchmark\.Memory\-pressure tasks hide or reduce opcode cues and require delayed state use\. Splits include seen tasks and seen lengths, seen tasks and held\-out lengths, held\-out tasks and seen lengths, and held\-out tasks and held\-out lengths\. The benchmark changes the inference problem\. Instead of reading a visible opcode from the instruction vector, the model must infer operation identity, address use and delayed writeback structure from register\-state transitions\. Degradation on held\-out memory\-pressure tasks therefore measures latent program induction under masked\-opcode conditions, not visible\-opcode program execution\.

Spiking variants\.Spiking variants replace or augment the controller hidden state with leaky integrate\-and\-fire or adaptive leaky integrate\-and\-fire dynamics\. One symbolic program step is expanded intoKKmicro\-steps\. The downstreamALUand register pathways remain non\-spiking\. The design keeps spikes in temporal controller memory while preserving deterministic non\-spiking arithmetic and writeback\.

Rollout\-level symbolic diagnostics\.[Figure˜4](https://arxiv.org/html/2607.10021#S3.F4)reports two trained open\-loop rollouts and one closed\-loop evaluation summary\. ColumnAuses the medium 16\-wideQAT8trained instance\. ColumnBuses the memory\-pressureQAT8ValueMemory trained instance with opcode masking as in the memory\-pressure data generator\. ColumnCuses the reference factorized multilayer\-perceptron candidate control evaluation log together with the paired candidate\-control summary metrics\.

For the open\-loop panels, the model receivesx1:Tx\_\{1:T\},r0r\_\{0\}and maskm1:Tm\_\{1:T\}for a program of lengthTT\. At each step theDCPUreturns gate logitsℓt\\ell\_\{t\}, gate probabilities, register tracertpredr^\{\\mathrm\{pred\}\}\_\{t\}and memory addressing weights\. The addressing weights correspond to Neural Turing Machine slots or value\-memory slots depending on the architecture\. Operation\-gate matchmtm\_\{t\}and router entropyHtH\_\{t\}follow the same definitions as in[section˜2\.6](https://arxiv.org/html/2607.10021#S2.SS6)withτ=0\.5\\tau=0\.5, hard gates andQAT8writeback when enabled\. Per\-step trace MAE usestrace\_mae\_by\_step\. Rollout exemplars are selected from fixed candidate seeds by maximizing gate agreement and minimizing mean trace MAE\. For the memory\-pressure rollout, structured memory addressing is also required\.

Each panel displays the non\-flat execution variable for the selected trace\. Ifmt≡1m\_\{t\}\\equiv 1, the gate and router row reportslog10⁡\(Ht\+ε\)\\log\_\{10\}\(H\_\{t\}\+\\varepsilon\)with the gate\-match summary\. If the reference opcode is constant, the opcode strip is represented by an in\-panel label\. If operation probabilities or Neural Turing Machine addressing are uniform, operand routing or per\-register trace MAE is shown instead\. Varying reference opcodes use a change\-point strip and vertical guides atotref≠ot−1refo\_\{t\}^\{\\mathrm\{ref\}\}\\neq o\_\{t\-1\}^\{\\mathrm\{ref\}\}transitions\.

For the closed\-loop panel, episode\-level evaluation records contain final MAE, success label, return, task family and the beam\-selected action sequence\. The beam uses width 4, depth 2 and up to 512 candidates per step\. Success isMAEfinal≤10−2\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\\leq 10^\{\-2\}\. The joint scatter uses a log\-binned hexbin for non\-success episodes plus a point overlay for successes\. Marginal histograms show densities split by success label, and the legend reports counts\. The per\-task bar chart uses the most frequent tasks in the evaluation log and encodes success rate with a left\-to\-right colormap plus numeric percent labels\. The paired\-lift panel reads the candidate\-control summary table and plots four paired comparisons: reference and learned\-QAT8backends, each for factorized multilayer perceptron and factorizedALIFspiking neural network\. Line style and marker distinguish multilayer perceptron versus spiking neural network\. Text annotations report the absolute success\-rate lift in percentage points\.

### 2\.6Rollout\-level spiking signal plots \([fig\.˜5](https://arxiv.org/html/2607.10021#S3.F5)\)

[Figure˜5](https://arxiv.org/html/2607.10021#S3.F5)analyzes the trained spiking ValueMemory instance used for the spiking rollout panels\. Memory\-pressure reference programs are built and executed by the reference CPU with optional opcode masking\. Specifically, when masking is enabled, the operation one\-hot prefix of each instruction vector is set to zero while register operands remain visible\.

##### Open\-loop forward evaluation \(panelsa–c\)\.

For a program of lengthTT, the model receives instruction tensorx1:Tx\_\{1:T\}, initial registersr0r\_\{0\}and padding maskm1:Tm\_\{1:T\}\. At each step the spiking ValueMemoryDCPUreturns gate logitsℓt\\ell\_\{t\}, gate probabilities \(hard or soft\), predicted registersrtpredr^\{\\mathrm\{pred\}\}\_\{t\}, micro\-step\-averaged spikesz¯t∈\[0,1\]H\\bar\{z\}\_\{t\}\\in\[0,1\]^\{H\}and membrane voltagesutu\_\{t\}\. Operation\-gate match is

mt=𝟏​\[arg⁡maxo∈𝒪⁡ℓt,o=otref\]\.m\_\{t\}=\\mathbf\{1\}\\\!\\left\[\\arg\\max\_\{o\\in\\mathcal\{O\}\}\\ell\_\{t,o\}=o\_\{t\}^\{\\mathrm\{ref\}\}\\right\]\.\(27\)The router entropy uses temperature\-scaled softmax probabilitiespt,o=softmax​\(ℓt/τ\)op\_\{t,o\}=\\mathrm\{softmax\}\(\\ell\_\{t\}/\\tau\)\_\{o\}with defaultτ=0\.5\\tau=0\.5:

Ht=−∑o∈𝒪pt,o​log⁡\(max⁡\(pt,o,10−12\)\),H\_\{t\}=\-\\sum\_\{o\\in\\mathcal\{O\}\}p\_\{t,o\}\\log\\\!\\left\(\\max\(p\_\{t,o\},10^\{\-12\}\)\\right\),\(28\)displayed aslog10⁡\(Ht\+ε\)\\log\_\{10\}\(H\_\{t\}\+\\varepsilon\)withε=10−4\\varepsilon=10^\{\-4\}\. Per\-step trace error follows:

MAEt=meanr,w​\|rt,r,wpred−rt,r,wref\|\\mathrm\{MAE\}\_\{t\}=\\mathrm\{mean\}\_\{r,w\}\\left\|r^\{\\mathrm\{pred\}\}\_\{t,r,w\}\-r^\{\\mathrm\{ref\}\}\_\{t,r,w\}\\right\|\(29\)over active padded steps\. Furthermore, the hidden units are reordered by descending mean spike rate𝔼t​\[z¯t,i\]\\mathbb\{E\}\_\{t\}\[\\bar\{z\}\_\{t,i\}\]for display\. As for the spike heatmaps, we have used values in\[0,1\]\[0,1\]with nearest\-neighbour interpolation\. The membrane heatmaps use a perceptually uniform sequential colormap with display limits set by the 2nd and 98th percentiles of the shown matrix\. The Opcode\-change vertical guides are drawn at steps whereotref≠ot−1refo\_\{t\}^\{\\mathrm\{ref\}\}\\neq o\_\{t\-1\}^\{\\mathrm\{ref\}\}, and trace reference lines use the stated MAE threshold for the corresponding panel\.

##### Three\-dimensional landscape \(panelc\)\.

Panelcplots the membrane matrixut,iu\_\{t,i\}as a surface over\(t,i\)\(t,i\)with the same unit ordering as panela\. Spike events withz¯t,i\>0\.5\\bar\{z\}\_\{t,i\}\>0\.5are rendered as markers slightly above the surface\. The subtitle reports mean spike rateρspike=\(T​H\)−1​∑t,iz¯t,i\\rho\_\{\\mathrm\{spike\}\}=\(TH\)^\{\-1\}\\sum\_\{t,i\}\\bar\{z\}\_\{t,i\}over the displayed rollout\.

##### Closed\-loop episode scatter \(paneld\)\.

Panelduses the episode\-level evaluation log from the reference factorized\-ALIFcandidate fine\-tuned instance\. Each row is one episode of the control environment\. Final MAE is

MAEfinal=meanr,w​\|Rr,w−Rr,w⋆\|,\\mathrm\{MAE\}^\{\\mathrm\{final\}\}=\\mathrm\{mean\}\_\{r,w\}\\left\|R\_\{r,w\}\-R^\{\\star\}\_\{r,w\}\\right\|,\(30\)and success is𝟏​\[MAEfinal≤ϵ\]\\mathbf\{1\}\[\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\\leq\\epsilon\]with defaultϵ=10−2\\epsilon=10^\{\-2\}\. Episode mean policy spike rate is the arithmetic mean of per\-step values recorded during the episode\. Failures are shown with a log\-scaled hexbin density, and successes are overlaid as green points with small horizontal jitter near zero MAE\. The marginal histograms show normalized densities of final MAE and spike rate split by success label\. Evaluation uses candidate action masking \(≤512\\leq 512actions\) and beam search with width 4 and depth 2, matching the candidate\-control protocol described above\.

### 2\.7Closed\-loop control objectives

Closed\-loop policies are trained by behaviour cloning followed by actor\-critic reinforcement learning\. We use A2C and PPO\-style variants\[[37](https://arxiv.org/html/2607.10021#bib.bib23),[45](https://arxiv.org/html/2607.10021#bib.bib22),[51](https://arxiv.org/html/2607.10021#bib.bib24)\]\. The transition backend is either the reference CPU transition or the learnedQAT8Neural CPU one\-step transition\. Candidate action sets and beam\-style evaluation are search constraints on top of the same transition semantics\. Because this protocol optimizes target\-reaching actions rather than replaying a supplied reference program, it is treated as a controllability extension to the trace\-supervised executor rather than as the primary execution benchmark\.

##### State, action and reward\.

The controller observation is the implemented vector:

st=\[vec​\(Rt\),vec​\(R⋆\),vec​\(R⋆−Rt\),H−tH,MAE​\(Rt,R⋆\)\],s\_\{t\}=\\left\[\\mathrm\{vec\}\(R\_\{t\}\),\\mathrm\{vec\}\(R^\{\\star\}\),\\mathrm\{vec\}\(R^\{\\star\}\-R\_\{t\}\),\\frac\{H\-t\}\{H\},\\mathrm\{MAE\}\(R\_\{t\},R^\{\\star\}\)\\right\],\(31\)whereRt∈\[0,1\]R×WR\_\{t\}\\in\[0,1\]^\{R\\times W\}is the current register file,R⋆R^\{\\star\}is the target register file andHHis the control horizon\. A symbolic action isat=\(ot,it,jt,dt\)a\_\{t\}=\(o\_\{t\},i\_\{t\},j\_\{t\},d\_\{t\}\)and is flattened exactly as

idx​\(at\)=\(\(\(ot​R\+it\)​R\+jt\)​R\+dt\)\.\\mathrm\{idx\}\(a\_\{t\}\)=\(\(\(o\_\{t\}R\+i\_\{t\}\)R\+j\_\{t\}\)R\+d\_\{t\}\)\.\(32\)The environment reward matches the implementation:

rt=10​\(MAEt−MAEt\+1\)−cstep−wE​E​\(ot\)\+𝟏done​\[𝟏succ​bsucc−\(1−𝟏succ\)​MAEt\+1\],r\_\{t\}=10\\left\(\\mathrm\{MAE\}\_\{t\}\-\\mathrm\{MAE\}\_\{t\+1\}\\right\)\-c\_\{\\mathrm\{step\}\}\-w\_\{E\}E\(o\_\{t\}\)\+\\mathbf\{1\}\_\{\\mathrm\{done\}\}\\left\[\\mathbf\{1\}\_\{\\mathrm\{succ\}\}b\_\{\\mathrm\{succ\}\}\-\(1\-\\mathbf\{1\}\_\{\\mathrm\{succ\}\}\)\\mathrm\{MAE\}\_\{t\+1\}\\right\],\(33\)with defaultcstep=0\.01c\_\{\\mathrm\{step\}\}=0\.01,bsucc=1b\_\{\\mathrm\{succ\}\}=1,wE=10−3w\_\{E\}=10^\{\-3\}and success thresholdMAEt\+1≤10−2\\mathrm\{MAE\}\_\{t\+1\}\\leq 10^\{\-2\}\. Thus the controller is rewarded for immediate target\-error reduction, penalized for step count and proxy operation cost, and given a terminal success bonus or terminal residual\-error penalty\.

##### Behaviour cloning\.

Oracle examples are collected from the task generator’s symbolic programs\. The flat behaviour\-cloning term is

ℒflat​\(θ\)=−1N​∑n=1Nlog⁡πθ𝒞​\(an⋆∣sn\),\\mathcal\{L\}\_\{\\mathrm\{flat\}\}\(\\theta\)=\-\\frac\{1\}\{N\}\\sum\_\{n=1\}^\{N\}\\log\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\_\{n\}^\{\\star\}\\mid s\_\{n\}\),\(34\)whereπθ𝒞\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}denotes the candidate\-masked categorical distribution when candidate masking is enabled\. For factorized policies, the implemented auxiliary loss decomposes the same action into operation, source\-register and destination\-register labels:

ℒfac=14​\[CE​\(ℓop,o⋆\)\+CE​\(ℓa,i⋆\)\+CE​\(ℓb,j⋆\)\+CE​\(ℓdst,d⋆\)\]\.\\mathcal\{L\}\_\{\\mathrm\{fac\}\}=\\frac\{1\}\{4\}\\left\[\\mathrm\{CE\}\(\\ell^\{\\mathrm\{op\}\},o^\{\\star\}\)\+\\mathrm\{CE\}\(\\ell^\{a\},i^\{\\star\}\)\+\\mathrm\{CE\}\(\\ell^\{b\},j^\{\\star\}\)\+\\mathrm\{CE\}\(\\ell^\{\\mathrm\{dst\}\},d^\{\\star\}\)\\right\]\.\(35\)Spiking policies add a rate regularizer\(ρ−ρ⋆\)2\(\\rho\-\\rho^\{\\star\}\)^\{2\}, whereρ\\rhois the policy’s last recorded mean spike rate andρ⋆\\rho^\{\\star\}is the configured target spike rate\. The behaviour\-cloning objective is therefore

ℒBC=ℒflat\+λfac​ℒfac\+λspike​\(ρ−ρ⋆\)2\.\\mathcal\{L\}\_\{\\mathrm\{BC\}\}=\\mathcal\{L\}\_\{\\mathrm\{flat\}\}\+\\lambda\_\{\\mathrm\{fac\}\}\\mathcal\{L\}\_\{\\mathrm\{fac\}\}\+\\lambda\_\{\\mathrm\{spike\}\}\(\\rho\-\\rho^\{\\star\}\)^\{2\}\.\(36\)

##### Actor\-critic objectives\.

For an episode reward sequence, discounted returns are

Gt=∑k=tTγk−t​rk,G\_\{t\}=\\sum\_\{k=t\}^\{T\}\\gamma^\{k\-t\}r\_\{k\},\(37\)and A2C advantagesA^t=Gt−Vϕ​\(st\)\\hat\{A\}\_\{t\}=G\_\{t\}\-V\_\{\\phi\}\(s\_\{t\}\)without normalizing them\. The implemented A2C loss is

ℒA2C=−1T∑tlogπθ𝒞\(at∣st\)stopgrad\(A^t\)\+cv1T∑t\(Vϕ\(st\)−Gt\)2−ch1T∑tH\(πθ𝒞\(⋅∣st\)\)\+λspike\(ρ−ρ⋆\)2\.\\mathcal\{L\}\_\{\\mathrm\{A2C\}\}=\-\\frac\{1\}\{T\}\\sum\_\{t\}\\log\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\_\{t\}\\mid s\_\{t\}\)\\,\\mathrm\{stopgrad\}\(\\hat\{A\}\_\{t\}\)\+c\_\{v\}\\frac\{1\}\{T\}\\sum\_\{t\}\(V\_\{\\phi\}\(s\_\{t\}\)\-G\_\{t\}\)^\{2\}\-c\_\{h\}\\frac\{1\}\{T\}\\sum\_\{t\}H\(\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(\\cdot\\mid s\_\{t\}\)\)\+\\lambda\_\{\\mathrm\{spike\}\}\(\\rho\-\\rho^\{\\star\}\)^\{2\}\.\(38\)For PPO, the collected trajectory log probabilities define the behaviour policy\. Advantages are normalized when the trajectory has more than one step, with a small numerical stabilizer\. We define the PPO likelihood ratio between the current candidate\-masked policy and the candidate\-masked behaviour policy that produced the logged trajectory as

ηtPPO​\(θ\)=πθ𝒞​\(at∣st\)πbeh𝒞​\(at∣st\)=exp⁡\[log⁡πθ𝒞​\(at∣st\)−log⁡πbeh𝒞​\(at∣st\)\]\.\\eta\_\{t\}^\{\\mathrm\{PPO\}\}\(\\theta\)=\\frac\{\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\_\{t\}\\mid s\_\{t\}\)\}\{\\pi\_\{\\mathrm\{beh\}\}^\{\\mathcal\{C\}\}\(a\_\{t\}\\mid s\_\{t\}\)\}=\\exp\\left\[\\log\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\_\{t\}\\mid s\_\{t\}\)\-\\log\\pi\_\{\\mathrm\{beh\}\}^\{\\mathcal\{C\}\}\(a\_\{t\}\\mid s\_\{t\}\)\\right\]\.\(39\)Here,πθ𝒞\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}is the current candidate\-masked policy,πbeh𝒞\\pi\_\{\\mathrm\{beh\}\}^\{\\mathcal\{C\}\}is the candidate\-masked behaviour policy recorded during rollout collection,ata\_\{t\}is the logged action andsts\_\{t\}is the controller state\. Values greater than one mean that the current policy assigns higher probability to the logged action than the behaviour policy did, whereas values below one mean that it assigns lower probability\. the implemented clipped actor term is

ℒPPO,actor=−1T​∑tmin⁡\(ηtPPO​\(θ\)​A^t,clip​\(ηtPPO​\(θ\),1−ϵclip,1\+ϵclip\)​A^t\),\\mathcal\{L\}\_\{\\mathrm\{PPO,actor\}\}=\-\\frac\{1\}\{T\}\\sum\_\{t\}\\min\\left\(\\eta\_\{t\}^\{\\mathrm\{PPO\}\}\(\\theta\)\\hat\{A\}\_\{t\},\\,\\mathrm\{clip\}\\\!\\left\(\\eta\_\{t\}^\{\\mathrm\{PPO\}\}\(\\theta\),1\-\\epsilon\_\{\\mathrm\{clip\}\},1\+\\epsilon\_\{\\mathrm\{clip\}\}\\right\)\\hat\{A\}\_\{t\}\\right\),\(40\)with the same value, entropy and spike\-rate terms as above\.

##### Factorized policy heads\.

The strongest closed\-loop runs use factorized action heads\. For a symbolic actiona=\(o,i,j,d\)a=\(o,i,j,d\), corresponding to operation, first source register, second source register and destination register, the factorized head scores the flat action by additive component logits,

Lθ​\(o,i,j,d∣s\)=ℓθop​\(o∣s\)\+ℓθa​\(i∣s\)\+ℓθb​\(j∣s\)\+ℓθdst​\(d∣s\)\.L\_\{\\theta\}\(o,i,j,d\\mid s\)=\\ell\_\{\\theta\}^\{\\mathrm\{op\}\}\(o\\mid s\)\+\\ell\_\{\\theta\}^\{a\}\(i\\mid s\)\+\\ell\_\{\\theta\}^\{b\}\(j\\mid s\)\+\\ell\_\{\\theta\}^\{\\mathrm\{dst\}\}\(d\\mid s\)\.\(41\)These joint logits are flattened back to the original action vocabulary before softmax, candidate masking and beam evaluation\. This formalism covers the multilayer\-perceptron, spiking\-ALIFand graph\-based factorized policies used in the closed\-loop experiments\.

##### Candidate control\.

Candidate control changes the action distribution but not the transition semantics\. The candidate generator first selects high\-error destination registers, always inserts simple symbolic primitives, and then ranks one\-step actions by

Scand​\(a\)=MAEafter​\(a\)−0\.15​max⁡\(0,MAEbefore−MAEafter​\(a\)\)\+0\.005​idx​\(o\)\.S\_\{\\mathrm\{cand\}\}\(a\)=\\mathrm\{MAE\}\_\{\\mathrm\{after\}\}\(a\)\-0\.15\\max\(0,\\mathrm\{MAE\}\_\{\\mathrm\{before\}\}\-\\mathrm\{MAE\}\_\{\\mathrm\{after\}\}\(a\)\)\+0\.005\\,\\mathrm\{idx\}\(o\)\.\(42\)The best actions up to the configured candidate budget are retained\. Invalid actions receive logit of−109\-10^\{9\}before softmax\. During evaluation, a beam of widthBbeamB\_\{\\mathrm\{beam\}\}maintains the highest\-scoring partial action sequences under the cumulative score

∑τ=tt\+D−1\[log⁡πθ𝒞​\(aτ∣sτ\)−10​MAE​\(F​\(sτ,aτ\),R⋆\)−wE​E​\(aτ\)\+𝟏​\[MAE​\(F​\(sτ,aτ\),R⋆\)≤ϵ\]\],\\sum\_\{\\tau=t\}^\{t\+D\-1\}\\left\[\\log\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\_\{\\tau\}\\mid s\_\{\\tau\}\)\-10\\,\\mathrm\{MAE\}\(F\(s\_\{\\tau\},a\_\{\\tau\}\),R^\{\\star\}\)\-w\_\{E\}E\(a\_\{\\tau\}\)\+\\mathbf\{1\}\[\\mathrm\{MAE\}\(F\(s\_\{\\tau\},a\_\{\\tau\}\),R^\{\\star\}\)\\leq\\epsilon\]\\right\],\(43\)whereDDis the configured beam depth, i\.e\. exactlyDDscore terms starting atτ=t\\tau=t\(one initial\-action term plusD−1D\-1expansion terms\)\. This is a constrained search procedure over the learned policy, not a new oracle\.

### 2\.8Mathematical and algorithmic details

All symbols below refer to tensors or operations in the reported simulator, with assumptions restricted to the simulation and replay protocols evaluated here\.

#### 2\.8\.1Symbolic CPU state

Let the register width beW∈\{8,16,32\}W\\in\\\{8,16,32\\\}, with the main experiments usingW=16W=16\. In this simulator, width is the length of a normalized continuous register vector, not an integer bit\-vector\. The register file containsRRregisters,

rt=\(rt,1,…,rt,R\)∈\[0,1\]R×W\.r\_\{t\}=\(r\_\{t,1\},\\ldots,r\_\{t,R\}\)\\in\[0,1\]^\{R\\times W\}\.\(44\)The notation “8\-bit”, “16\-bit” and “32\-bit” follows the profile names used during experimentation, but the reference transition uses continuous vectors in\[0,1\]\[0,1\]and continuous operation proxies\. Quantization experiments then projectALUwriteback values onto an 8\-bit grid\.

We have used the following operation set:

𝒪=\{AND,OR,XOR,ADD,SUB,SHL,SHR,MUL\},\\mathcal\{O\}=\\\{\\mathrm\{AND\},\\mathrm\{OR\},\\mathrm\{XOR\},\\mathrm\{ADD\},\\mathrm\{SUB\},\\mathrm\{SHL\},\\mathrm\{SHR\},\\mathrm\{MUL\}\\\},\(45\)with extended task families using combinations and memory\-mediated patterns\. Each instruction is a tuple

ξt=\(ot,it,jt,dt\),\\xi\_\{t\}=\(o\_\{t\},i\_\{t\},j\_\{t\},d\_\{t\}\),\(46\)whereot∈𝒪o\_\{t\}\\in\\mathcal\{O\}is the opcode,it,jt,dt∈\{0,…,R−1\}i\_\{t\},j\_\{t\},d\_\{t\}\\in\\\{0,\\ldots,R\-1\\\}are zero\-based source and destination register indices\. Dataset context such as padding masks, task labels, energy\-choice policies and alternative traces is stored in separate arrays, not inside the encoded instruction vector\.

The deterministic reference\-interpreter transition used to generate the training and evaluation trajectories isrt=𝒯​\(rt−1,ξt\)r\_\{t\}=\\mathcal\{T\}\(r\_\{t\-1\},\\xi\_\{t\}\), where the reference interpreter itself does not use neural memory\. For each instruction,rt,dt=ALUot​\(rt−1,it,rt−1,jt\)r\_\{t,d\_\{t\}\}=\\mathrm\{ALU\}\_\{o\_\{t\}\}\(r\_\{t\-1,i\_\{t\}\},r\_\{t\-1,j\_\{t\}\}\)andrt,j=rt−1,jr\_\{t,j\}=r\_\{t\-1,j\}forj≠dtj\\neq d\_\{t\}\. The implemented continuous operation bank is given by:

AAND​\(u,v\)\\displaystyle A\_\{\\mathrm\{AND\}\}\(u,v\)=clip​\(u⊙v,0,1\),\\displaystyle=\\mathrm\{clip\}\(u\\odot v,0,1\),\(47\)AOR​\(u,v\)\\displaystyle A\_\{\\mathrm\{OR\}\}\(u,v\)=max⁡\(u,v\),\\displaystyle=\\max\(u,v\),\(48\)AXOR​\(u,v\)\\displaystyle A\_\{\\mathrm\{XOR\}\}\(u,v\)=\|u−v\|,\\displaystyle=\|u\-v\|,\(49\)AADD​\(u,v\)\\displaystyle A\_\{\\mathrm\{ADD\}\}\(u,v\)=clip​\(u\+v,0,1\),\\displaystyle=\\mathrm\{clip\}\(u\+v,0,1\),\(50\)ASUB​\(u,v\)\\displaystyle A\_\{\\mathrm\{SUB\}\}\(u,v\)=clip​\(u−v,0,1\),\\displaystyle=\\mathrm\{clip\}\(u\-v,0,1\),\(51\)ASHL​\(u,v\)\\displaystyle A\_\{\\mathrm\{SHL\}\}\(u,v\)=clip​\(2​u,0,1\),\\displaystyle=\\mathrm\{clip\}\(2u,0,1\),\(52\)ASHR​\(u,v\)\\displaystyle A\_\{\\mathrm\{SHR\}\}\(u,v\)=0\.5​u,\\displaystyle=0\.5u,\(53\)AMUL​\(u,v\)\\displaystyle A\_\{\\mathrm\{MUL\}\}\(u,v\)=clip​\(u⊙v,0,1\)\.\\displaystyle=\\mathrm\{clip\}\(u\\odot v,0,1\)\.\(54\)These names are symbolic labels for differentiable CPU\-like operations\. They are not claims of exact integer bitwise execution in the present implementation\. The training dataset contains the full reference trace

\{Xinstr\(n\),r0\(n\),r1:T\(n\),rT\(n\),o1:T\(n\),e1:T\(n\),δ1:T\(n\),m1:T\(n\)\}n=1N,\\left\\\{X\_\{\\mathrm\{instr\}\}^\{\(n\)\},r\_\{0\}^\{\(n\)\},r\_\{1:T\}^\{\(n\)\},r\_\{T\}^\{\(n\)\},o\_\{1:T\}^\{\(n\)\},e\_\{1:T\}^\{\(n\)\},\\delta\_\{1:T\}^\{\(n\)\},m\_\{1:T\}^\{\(n\)\}\\right\\\}\_\{n=1\}^\{N\},\(55\)whereXinstrX\_\{\\mathrm\{instr\}\}is the encoded instruction sequence,ete\_\{t\}andδt\\delta\_\{t\}are simulation proxy energy and delay traces, andmtm\_\{t\}is the padding mask\.

#### 2\.8\.2Instruction encoding

Each instruction is encoded as the concatenation of an operation one\-hot vector and normalized source/destination register indices\. LetDR=max⁡\(1,R−1\)D\_\{R\}=\\max\(1,R\-1\)denote the guarded denominator used for register\-index normalization:

xt=\[onehot​\(ot\);itDR;jtDR;dtDR\]∈ℝ\|𝒪\|\+3\.x\_\{t\}=\\left\[\\mathrm\{onehot\}\(o\_\{t\}\);\\frac\{i\_\{t\}\}\{D\_\{R\}\};\\frac\{j\_\{t\}\}\{D\_\{R\}\};\\frac\{d\_\{t\}\}\{D\_\{R\}\}\\right\]\\in\\mathbb\{R\}^\{\|\\mathcal\{O\}\|\+3\}\.\(56\)The model then applies a learned linear encoder,

ϕt=ReLU​\(Wenc​xt\+benc\)\.\\phi\_\{t\}=\\mathrm\{ReLU\}\(W\_\{\\mathrm\{enc\}\}x\_\{t\}\+b\_\{\\mathrm\{enc\}\}\)\.\(57\)Decoding rounds and clips the final three normalized entries:

\(i^t,j^t,d^t\)=clip​\(round​\(DR​xt,−3:\),0,R−1\)\.\(\\hat\{i\}\_\{t\},\\hat\{j\}\_\{t\},\\hat\{d\}\_\{t\}\)=\\mathrm\{clip\}\\left\(\\mathrm\{round\}\(D\_\{R\}x\_\{t,\-3:\}\),0,R\-1\\right\)\.\(58\)When padding is present, a binary maskmt∈\{0,1\}m\_\{t\}\\in\\\{0,1\\\}determines whether the step updates the register state and contributes to masked trace/gate losses\. The implementation masks the state update and loss terms rather than redefining the logits themselves:

r^t=mt​r^tstep\+\(1−mt\)​r^t−1,ℒG∝∑tmt​CE​\(ℓt,ot\)\.\\hat\{r\}\_\{t\}=m\_\{t\}\\,\\hat\{r\}\_\{t\}^\{\\mathrm\{step\}\}\+\(1\-m\_\{t\}\)\\,\\hat\{r\}\_\{t\-1\},\\qquad\\mathcal\{L\}\_\{G\}\\propto\\sum\_\{t\}m\_\{t\}\\,\\mathrm\{CE\}\(\\ell\_\{t\},o\_\{t\}\)\.\(59\)Here,r^tstep\\hat\{r\}\_\{t\}^\{\\mathrm\{step\}\}is the register state that would be produced by executing the instruction at stepttbefore applying the padding mask\. Whenmt=1m\_\{t\}=1, the step contains a real instruction, so the candidate update is kept and the gate loss contributes to training\. Whenmt=0m\_\{t\}=0, the position is only a batching placeholder used to align programs of different lengths\. In that case, the previous register state is copied forward and the gate target at that position is ignored\.

The logitsℓt\\ell\_\{t\}are not redefined for padded steps\. They may still be computed by the unrolled network, but the mask prevents the resulting candidate update from changing the register state and prevents that step from contributing to the supervised losses\. Padding is therefore a batching convention, not an additional symbolic instruction and not a learned no\-op\. In batched notation, the same rule is applied usingmn,tm\_\{n,t\}, and losses are normalized over the active\-step count

Nm=∑n,tmn,t\.N\_\{m\}=\\sum\_\{n,t\}m\_\{n,t\}\.The effective final state for sequencennis taken at its last active step,

Tn=max⁡\{t∣mn,t=1\}\.T\_\{n\}=\\max\\\{t\\mid m\_\{n,t\}=1\\\}\.

#### 2\.8\.3Controller recurrence

The reference model uses a standardGRUcontroller\[[7](https://arxiv.org/html/2607.10021#bib.bib18)\]\. Letqtq\_\{t\}be theNTMread vector andϕt\\phi\_\{t\}the encoded instruction\. The recurrent input is

gt=\[ϕt;qt\]\.g\_\{t\}=\[\\phi\_\{t\};q\_\{t\}\]\.\(60\)The previous register values do not enter the GRU input directly in the implemented primary model\. They enter theALUrouter through the selected operands\. The hidden state evolves according to the update\-gate convention, in which the update gateztz\_\{t\}weights the*previous*hidden state rather than the candidate:

zt\\displaystyle z\_\{t\}=σ​\(Wz​gt\+Uz​ht−1\+bz\),\\displaystyle=\\sigma\(W\_\{z\}g\_\{t\}\+U\_\{z\}h\_\{t\-1\}\+b\_\{z\}\),\(61\)qtgru\\displaystyle q\_\{t\}^\{\\mathrm\{gru\}\}=σ​\(Wq​gt\+Uq​ht−1\+bq\),\\displaystyle=\\sigma\(W\_\{q\}g\_\{t\}\+U\_\{q\}h\_\{t\-1\}\+b\_\{q\}\),\(62\)h~t\\displaystyle\\tilde\{h\}\_\{t\}=tanh⁡\(Wh​gt\+Uh​\(qtgru⊙ht−1\)\+bh\),\\displaystyle=\\tanh\(W\_\{h\}g\_\{t\}\+U\_\{h\}\(q\_\{t\}^\{\\mathrm\{gru\}\}\\odot h\_\{t\-1\}\)\+b\_\{h\}\),\(63\)ht\\displaystyle h\_\{t\}=\(1−zt\)⊙h~t\+zt⊙ht−1\.\\displaystyle=\(1\-z\_\{t\}\)\\odot\\tilde\{h\}\_\{t\}\+z\_\{t\}\\odot h\_\{t\-1\}\.\(64\)The architecture comparison substitutes this controller with transformer, temporal convolution, graph, temporal graph and state\-space alternatives\[[55](https://arxiv.org/html/2607.10021#bib.bib11),[3](https://arxiv.org/html/2607.10021#bib.bib12),[27](https://arxiv.org/html/2607.10021#bib.bib13),[4](https://arxiv.org/html/2607.10021#bib.bib14),[16](https://arxiv.org/html/2607.10021#bib.bib15)\]\.

#### 2\.8\.4Operation gates

The gatedALUrouter emits logits over the operation set from the concatenated source operands, auxiliary controller projection and opcode hint:

ut=r^t−1,it,vt=r^t−1,jt,u\_\{t\}=\\hat\{r\}\_\{t\-1,i\_\{t\}\},\\qquad v\_\{t\}=\\hat\{r\}\_\{t\-1,j\_\{t\}\},\(65\)whereut,vt∈\[0,1\]Wu\_\{t\},v\_\{t\}\\in\[0,1\]^\{W\}are operand vectors read from the current predicted register state, andit,jti\_\{t\},j\_\{t\}are the corresponding source\-register indices\. The router is

ℓt=frouter​\(\[ut;vt;auxt;onehot​\(ot\)\]\),ℓt∈ℝ\|𝒪\|\.\\ell\_\{t\}=f\_\{\\mathrm\{router\}\}\\\!\\left\(\[u\_\{t\};v\_\{t\};\\mathrm\{aux\}\_\{t\};\\mathrm\{onehot\}\(o\_\{t\}\)\]\\right\),\\qquad\\ell\_\{t\}\\in\\mathbb\{R\}^\{\|\\mathcal\{O\}\|\}\.\(66\)Here,

auxt=tanh⁡\(Waux​ht\+baux\),\\mathrm\{aux\}\_\{t\}=\\tanh\(W\_\{\\mathrm\{aux\}\}h\_\{t\}\+b\_\{\\mathrm\{aux\}\}\),\(67\)andfrouterf\_\{\\mathrm\{router\}\}is a two\-layer multilayer perceptron with ReLU activation\.

The opcode one\-hot vectoronehot​\(ot\)\\mathrm\{onehot\}\(o\_\{t\}\)is available to the router in the visible\-opcode execution regime\. Gate agreement in this setting therefore measures whether the model preserves and executes the supplied symbolic instruction through the named operation path\. It does not measure recovery of an unobserved opcode\. Operation inference without this cue is evaluated separately in the hidden\-opcode memory\-pressure benchmark\.

Soft execution uses the temperature\-scaled gate distribution

πtsoft=softmax​\(ℓt/τ\),\\pi\_\{t\}^\{\\mathrm\{soft\}\}=\\mathrm\{softmax\}\(\\ell\_\{t\}/\\tau\),\(68\)whereτ\>0\\tau\>0is the gate temperature\. During stochastic training, the Gumbel–Softmax relaxation is used\[[25](https://arxiv.org/html/2607.10021#bib.bib46),[36](https://arxiv.org/html/2607.10021#bib.bib16)\]:

πt,kgumbel=exp⁡\(\(ℓt,k\+gt,k\)/τ\)∑jexp⁡\(\(ℓt,j\+gt,j\)/τ\),\\pi\_\{t,k\}^\{\\mathrm\{gumbel\}\}=\\frac\{\\exp\\\!\\left\(\(\\ell\_\{t,k\}\+g\_\{t,k\}\)/\\tau\\right\)\}\{\\sum\_\{j\}\\exp\\\!\\left\(\(\\ell\_\{t,j\}\+g\_\{t,j\}\)/\\tau\\right\)\},\(69\)with

gt,k=−log⁡\[−log⁡qt,k\],qt,k∼Uniform​\(0,1\)\.g\_\{t,k\}=\-\\log\[\-\\log q\_\{t,k\}\],\\qquad q\_\{t,k\}\\sim\\mathrm\{Uniform\}\(0,1\)\.\(70\)The auxiliary variableqt,kq\_\{t,k\}is used here to avoid confusion with the operand vectorutu\_\{t\}\.

Hard deterministic evaluation uses

o^t=arg​maxk​ℓt,k,πt,khard=𝟏​\[k=o^t\]\.\\hat\{o\}\_\{t\}=\\mathrm\{arg\\,max\}\_\{k\}\\ell\_\{t,k\},\\qquad\\pi\_\{t,k\}^\{\\mathrm\{hard\}\}=\\mathbf\{1\}\[k=\\hat\{o\}\_\{t\}\]\.\(71\)This separation provides a stochastic differentiable routing mechanism during training and a deterministic, auditable symbolic operation path during evaluation\.

##### Straight\-through hardening\.

For diagnostic runs using deterministic straight\-through hardening, the gate can be written as

πtST=sg​\(πthard−πtsoft\)\+πtsoft,\\pi\_\{t\}^\{\\mathrm\{ST\}\}=\\mathrm\{sg\}\\\!\\left\(\\pi\_\{t\}^\{\\mathrm\{hard\}\}\-\\pi\_\{t\}^\{\\mathrm\{soft\}\}\\right\)\+\\pi\_\{t\}^\{\\mathrm\{soft\}\},\(72\)wheresg​\(⋅\)\\mathrm\{sg\}\(\\cdot\)stops gradients\. The forward pass uses the discrete hard gate, while the backward pass follows the soft relaxation\. Deterministic hardening and stochastic Gumbel training serve different purposes rather than representing competing scientific claims\. Gumbel–Softmax supplies a stochastic differentiable routing mechanism during optimization, while deterministic gates provide reproducible execution audits\. Hard execution is therefore treated as the interpretable evaluation and deployment\-facing mode\.

##### Gate margin\.

Let

kt\(1\)=arg​maxk​πt,ksoftk\_\{t\}^\{\(1\)\}=\\mathrm\{arg\\,max\}\_\{k\}\\pi\_\{t,k\}^\{\\mathrm\{soft\}\}\(73\)denote the most probable operation, and let

kt\(2\)=arg​maxj≠kt\(1\)​πt,jsoftk\_\{t\}^\{\(2\)\}=\\mathrm\{arg\\,max\}\_\{j\\neq k\_\{t\}^\{\(1\)\}\}\\pi\_\{t,j\}^\{\\mathrm\{soft\}\}\(74\)denote the second\-most probable operation\. The gate confidence margin is

μt=πt,kt\(1\)soft−πt,kt\(2\)soft\.\\mu\_\{t\}=\\pi\_\{t,k\_\{t\}^\{\(1\)\}\}^\{\\mathrm\{soft\}\}\-\\pi\_\{t,k\_\{t\}^\{\(2\)\}\}^\{\\mathrm\{soft\}\}\.\(75\)A large margin indicates that the selected symbolic operation is well separated from the nearest alternative\. The margin is therefore a diagnostic of routing confidence and sensitivity to perturbations of the router logits or gate probabilities\. In the present QAT8 implementation, quantization is applied to the selected ALU value or writeback pathway rather than to the router logits\. Gate margin should consequently not be interpreted as a direct bound on writeback\-quantization error\.

#### 2\.8\.5Mixture ALU

For each possible operationk∈𝒪k\\in\\mathcal\{O\}, the model computes a candidate register result using the same continuous operation bank as the reference interpreter:

yt,k=Ak​\(r^t−1,it,r^t−1,jt\),y\_\{t,k\}=A\_\{k\}\\\!\\left\(\\hat\{r\}\_\{t\-1,i\_\{t\}\},\\hat\{r\}\_\{t\-1,j\_\{t\}\}\\right\),\(76\)whereAkA\_\{k\}is not a learned arithmetic head in the primary executor\. This term is a fixed differentiable operation\. Soft execution writes

y^tsoft=∑k∈𝒪πt,k​yt,k\.\\hat\{y\}\_\{t\}^\{\\mathrm\{soft\}\}=\\sum\_\{k\\in\\mathcal\{O\}\}\\pi\_\{t,k\}y\_\{t,k\}\.\(77\)Hard execution writes

y^thard=yt,o^t\.\\hat\{y\}\_\{t\}^\{\\mathrm\{hard\}\}=y\_\{t,\\hat\{o\}\_\{t\}\}\.\(78\)The destination update is masked:

r^t,j=\(1−wt,j\)​r^t−1,j\+wt,j​y^t,wt,j=𝟏​\[j=dt\]\.\\hat\{r\}\_\{t,j\}=\(1\-w\_\{t,j\}\)\\hat\{r\}\_\{t\-1,j\}\+w\_\{t,j\}\\hat\{y\}\_\{t\},\\qquad w\_\{t,j\}=\\mathbf\{1\}\[j=d\_\{t\}\]\.\(79\)For padding steps,r^t=r^t−1\\hat\{r\}\_\{t\}=\\hat\{r\}\_\{t\-1\}\.

##### Locality of the write rule\.

The write equation enforces a CPU\-like locality constraint: one instruction updates the destination register and leaves non\-destination registers unchanged\. Without this constraint, a black\-box sequence model can distribute a small amount of error correction across all registers\. Such behaviour may improve final loss but destroys the auditability of the transition\. The write mask therefore acts as an inductive bias and as a verification surface\. Trace faithfulness can be decomposed into destination error and preservation error:

MAEdst\\displaystyle\\mathrm\{MAE\}\_\{\\mathrm\{dst\}\}=1Nm​W​∑n,t,kmn,t​\|r^t,dn,t,k\(n\)−rt,dn,t,k\(n\)\|,\\displaystyle=\\frac\{1\}\{N\_\{m\}W\}\\sum\_\{n,t,k\}m\_\{n,t\}\|\\hat\{r\}\_\{t,d\_\{n,t\},k\}^\{\(n\)\}\-r\_\{t,d\_\{n,t\},k\}^\{\(n\)\}\|,\(80\)MAEpreserve\\displaystyle\\mathrm\{MAE\}\_\{\\mathrm\{preserve\}\}=1Nm​\(R−1\)​W​∑n,t,j≠dn,t,kmn,t​\|r^t,j,k\(n\)−rt,j,k\(n\)\|\.\\displaystyle=\\frac\{1\}\{N\_\{m\}\(R\-1\)W\}\\sum\_\{n,t,j\\neq d\_\{n,t\},k\}m\_\{n,t\}\|\\hat\{r\}\_\{t,j,k\}^\{\(n\)\}\-r\_\{t,j,k\}^\{\(n\)\}\|\.\(81\)HereNm=∑n,tmn,tN\_\{m\}=\\sum\_\{n,t\}m\_\{n,t\}is the active\-step count, anddn,td\_\{n,t\}is the zero\-based destination register index decoded for samplennat steptt\. A faithful executor should make both quantities small, and a final\-state imitator can hide preservation errors until they accumulate\.

#### 2\.8\.6Implemented differentiable ALU bank

TheALUbank is shared by the reference interpreter and the model\. The model does not learn independent operation\-specific arithmetic heads for the main executor\. Instead, it learns the router that chooses among fixed continuous operations:

Yt=\[ut⊙vt,max⁡\(ut,vt\),\|ut−vt\|,ut\+vt,ut−vt,2​ut,0\.5​ut,ut⊙vt\],Y\_\{t\}=\\left\[u\_\{t\}\\odot v\_\{t\},\\ \\max\(u\_\{t\},v\_\{t\}\),\\ \|u\_\{t\}\-v\_\{t\}\|,\\ u\_\{t\}\+v\_\{t\},\\ u\_\{t\}\-v\_\{t\},\\ 2u\_\{t\},\\ 0\.5u\_\{t\},\\ u\_\{t\}\\odot v\_\{t\}\\right\],\(82\)followed by clipping to\[0,1\]\[0,1\]\. The operation labelsAND,OR,XOR,ADD,SUB,SHL,SHRandMULname these continuous CPU\-like operations\. This point is essential for interpretability: the present study tests faithful execution of the differentiable reference interpreter, not exact emulation of integer bitwise arithmetic\. The current continuous proxies also makeANDandMULidentical at the value\-transition level, because both are implemented as elementwise multiplication\. They remain distinct supervised symbolic labels in gate space, but not distinct arithmetic maps in this version of the reference interpreter\.

#### 2\.8\.7Differentiable memory

Memory\-augmented variants use anNTM\-style memory\[[13](https://arxiv.org/html/2607.10021#bib.bib9),[14](https://arxiv.org/html/2607.10021#bib.bib10)\]\. LetMt∈ℝS×DM\_\{t\}\\in\\mathbb\{R\}^\{S\\times D\}containSSslots of dimensionDD\. A content keyktk\_\{t\}and strengthβt\\beta\_\{t\}define content weights

ct,i=exp⁡\(βt​cos⁡\(kt,Mt−1,i\)\)∑j=1Sexp⁡\(βt​cos⁡\(kt,Mt−1,j\)\)\.c\_\{t,i\}=\\frac\{\\exp\(\\beta\_\{t\}\\,\\cos\(k\_\{t\},M\_\{t\-1,i\}\)\)\}\{\\sum\_\{j=1\}^\{S\}\\exp\(\\beta\_\{t\}\\,\\cos\(k\_\{t\},M\_\{t\-1,j\}\)\)\}\.\(83\)The memory\-addressing rule then applies a learned three\-way circular shift mixture over left, stay and right positions:

αt=st,−1​roll\+1​\(ct\)\+st,0​ct\+st,\+1​roll−1​\(ct\),st=softmax​\(Ws​ht\+bs\)\.\\alpha\_\{t\}=s\_\{t,\-1\}\\,\\mathrm\{roll\}\_\{\+1\}\(c\_\{t\}\)\+s\_\{t,0\}\\,c\_\{t\}\+s\_\{t,\+1\}\\,\\mathrm\{roll\}\_\{\-1\}\(c\_\{t\}\),\\qquad s\_\{t\}=\\mathrm\{softmax\}\(W\_\{s\}h\_\{t\}\+b\_\{s\}\)\.\(84\)The read vector is

qt=∑i=1Sαt,i​Mt−1,i\.q\_\{t\}=\\sum\_\{i=1\}^\{S\}\\alpha\_\{t,i\}M\_\{t\-1,i\}\.\(85\)Write operations use erase and add vectorset,vtadd∈ℝDe\_\{t\},v\_\{t\}^\{\\mathrm\{add\}\}\\in\\mathbb\{R\}^\{D\}:

Mt,i=Mt−1,i⊙\(1−ωt,i​et\)\+ωt,i​vtadd,M\_\{t,i\}=M\_\{t\-1,i\}\\odot\(1\-\\omega\_\{t,i\}e\_\{t\}\)\+\\omega\_\{t,i\}v\_\{t\}^\{\\mathrm\{add\}\},\(86\)whereωt\\omega\_\{t\}is a learned write distribution\. No\-memory ablations setqt=0q\_\{t\}=0and skip the memory update, while value\-memory variants expose value\-addressable pathways for hidden\-opcode memory\-pressure tasks\.

#### 2\.8\.8Quantization\-simulated execution

TheQAT8mode applies quantization simulation to the selectedALUoutput\. In the standard models this tensor is the value written to the destination register, so it is also the writeback tensor\. In value\-memory variants, the same round\-and\-clamp quantization simulator is applied before the later value\-memory blend, which is clamped but not re\-quantized\. For a tensorx∈\[0,1\]x\\in\[0,1\]andBBquantization bits, the projection is

QB​\(x\)=clip​\(round​\(x​\(2B−1\)\),0,2B−1\)2B−1\.Q\_\{B\}\(x\)=\\frac\{\\mathrm\{clip\}\\left\(\\mathrm\{round\}\(x\(2^\{B\}\-1\)\),0,2^\{B\}\-1\\right\)\}\{2^\{B\}\-1\}\.\(87\)ForQAT8,B=8B=8\. The simulator uses this direct round\-and\-clamp projection\. Therefore, it does not implement signed zero\-points, per\-channel weight quantization or a custom straight\-through estimator for the quantizer\. Consequently, once quantization simulation is active, gradients through roundedALUvalues are not replaced by a custom surrogate\. The termQAT8in this manuscript therefore denotes training/evaluation with quantized forwardALUsimulation and optional warmup, not a complete integer\-only deployment recipe\. QAT warmup delays quantization simulation for the firstEwE\_\{w\}epochs, allowing the continuous model to learn stable gate and trace structure before low\-precisionALUsimulation is introduced\.

The key evaluation distinction is between continuous\-reference scoring and matched fixed\-point replay\. Continuous\-reference scoring compares theQAT8model against the full\-precision reference trace\. Matched replay quantizes the reference semantics to the same fixed\-point representation used by the quantization\-simulated writeback\. A low\-precision model may show continuous drift yet be exact under the replay semantics\. This distinction is essential for defensible device\-facing claims\.

##### Matched fixed\-point replay criterion\.

LetQBQ\_\{B\}be the fixed\-point projection induced by the writeback quantizer and let𝒯\\mathcal\{T\}be the continuous reference transition\. The matched replay replays the same instruction stream, leaves initial registers at input precision and quantizes each executed destination update:

𝒯B​\(r,x\)=Writed​\(r,QB​\(Ao​\(ri,rj\)\)\)\.\\mathcal\{T\}\_\{B\}\(r,x\)=\\mathrm\{Write\}\_\{d\}\\\!\\left\(r,Q\_\{B\}\(A\_\{o\}\(r\_\{i\},r\_\{j\}\)\)\\right\)\.\(88\)TheQAT8model transition isFθ,BF\_\{\\theta,B\}\. We say that a trajectory is replay faithful if

Fθ,B\(t\)​\(r0,x1:t\)=𝒯B\(t\)​\(r0,x1:t\)∀t≤T\.F\_\{\\theta,B\}^\{\(t\)\}\(r\_\{0\},x\_\{1:t\}\)=\\mathcal\{T\}\_\{B\}^\{\(t\)\}\(r\_\{0\},x\_\{1:t\}\)\\quad\\forall t\\leq T\.\(89\)Continuous\-reference MAE instead comparesFθ,B\(t\)F\_\{\\theta,B\}^\{\(t\)\}with𝒯\(t\)\\mathcal\{T\}^\{\(t\)\}\. The two targets differ by the quantization residual

ϵt=𝒯\(t\)​\(r0,x1:t\)−𝒯B\(t\)​\(r0,x1:t\)\.\\epsilon\_\{t\}=\\mathcal\{T\}^\{\(t\)\}\(r\_\{0\},x\_\{1:t\}\)\-\\mathcal\{T\}\_\{B\}^\{\(t\)\}\(r\_\{0\},x\_\{1:t\}\)\.\(90\)By the triangle inequality,

‖Fθ,B\(t\)−𝒯\(t\)‖1≤‖Fθ,B\(t\)−𝒯B\(t\)‖1\+‖ϵt‖1\.\\\|F\_\{\\theta,B\}^\{\(t\)\}\-\\mathcal\{T\}^\{\(t\)\}\\\|\_\{1\}\\leq\\\|F\_\{\\theta,B\}^\{\(t\)\}\-\\mathcal\{T\}\_\{B\}^\{\(t\)\}\\\|\_\{1\}\+\\\|\\epsilon\_\{t\}\\\|\_\{1\}\.\(91\)Thus non\-zero continuous MAE is expected even when the first term is zero\. The manuscript therefore reports both continuous\-reference drift and matched fixed\-point replay faithfulness\.

##### Quantization error bound\.

For a uniform scalar quantizer with step sizess, each scalar projection satisfies

\|Q​\(x\)−x\|≤s2\|Q\(x\)\-x\|\\leq\\frac\{s\}\{2\}\(92\)away from saturation\. If a register vector hasDDscalar components, the per\-registerℓ1\\ell\_\{1\}projection error is bounded byD​s/2Ds/2\. Saturation violates this simple bound, which is why the implementation records the deployment profile and uses matched\-reference scoring rather than relying only on an analytic quantization bound\.

#### 2\.8\.9Training objective

The full loss is

ℒ=λF​ℒF\+λT​ℒT\+λG​ℒG\+λH​ℒH\+λS​ℒS\+λE​ℒE\+λD​ℒD\+λZ​ℒZ\.\\mathcal\{L\}=\\lambda\_\{F\}\\mathcal\{L\}\_\{F\}\+\\lambda\_\{T\}\\mathcal\{L\}\_\{T\}\+\\lambda\_\{G\}\\mathcal\{L\}\_\{G\}\+\\lambda\_\{H\}\\mathcal\{L\}\_\{H\}\+\\lambda\_\{S\}\\mathcal\{L\}\_\{S\}\+\\lambda\_\{E\}\\mathcal\{L\}\_\{E\}\+\\lambda\_\{D\}\\mathcal\{L\}\_\{D\}\+\\lambda\_\{Z\}\\mathcal\{L\}\_\{Z\}\.\(93\)Letmn,t∈\{0,1\}m\_\{n,t\}\\in\\\{0,1\\\}be the padding mask and let

Nm=∑n,tmn,t\.N\_\{m\}=\\sum\_\{n,t\}m\_\{n,t\}\.\(94\)Training uses global masked means over active timesteps and tensor elements, not a per\-sequence average\. The final\-state loss is

ℒF=1NB​R​W​∑n=1NB‖r^Tn\(n\)−rTn\(n\)‖1,\\mathcal\{L\}\_\{F\}=\\frac\{1\}\{N\_\{B\}RW\}\\sum\_\{n=1\}^\{N\_\{B\}\}\\left\\\|\\hat\{r\}\_\{T\_\{n\}\}^\{\(n\)\}\-r\_\{T\_\{n\}\}^\{\(n\)\}\\right\\\|\_\{1\},\(95\)whereNBN\_\{B\}is the mini\-batch size\. The trace loss is

ℒT=∑n,tmn,t​‖r^t\(n\)−rt\(n\)‖1Nm​R​W\.\\mathcal\{L\}\_\{T\}=\\frac\{\\sum\_\{n,t\}m\_\{n,t\}\\left\\\|\\hat\{r\}\_\{t\}^\{\(n\)\}\-r\_\{t\}^\{\(n\)\}\\right\\\|\_\{1\}\}\{N\_\{m\}RW\}\.\(96\)Gate supervision is cross\-entropy over the active flattened timesteps:

ℒG=−1Nm​∑n,tmn,t​log⁡πt,ot\(n\)\.\\mathcal\{L\}\_\{G\}=\-\\frac\{1\}\{N\_\{m\}\}\\sum\_\{n,t\}m\_\{n,t\}\\log\\pi\_\{t,o\_\{t\}\}^\{\(n\)\}\.\(97\)Entropy regularization is

ℒH=−1Nm​∑n,tmn,t​∑k∈𝒪πt,k\(n\)​log⁡πt,k\(n\)\.\\mathcal\{L\}\_\{H\}=\-\\frac\{1\}\{N\_\{m\}\}\\sum\_\{n,t\}m\_\{n,t\}\\sum\_\{k\\in\\mathcal\{O\}\}\\pi\_\{t,k\}^\{\(n\)\}\\log\\pi\_\{t,k\}^\{\(n\)\}\.\(98\)Because the total loss adds\+λH​ℒH\+\\lambda\_\{H\}\\mathcal\{L\}\_\{H\}withλH\>0\\lambda\_\{H\}\>0in the reported runs, this term penalizes high\-entropy gates and encourages sharper operation choices\. It is not an entropy\-bonus exploration term\. Gate\-smoothness regularization is the active\-pair mean of the mean absolute operation\-wise difference:

ℒS=∑n,t≥2mn,t​mn,t−1​1\|𝒪\|​∑k∈𝒪\|πt,k\(n\)−πt−1,k\(n\)\|∑n,t≥2mn,t​mn,t−1\.\\mathcal\{L\}\_\{S\}=\\frac\{\\sum\_\{n,t\\geq 2\}m\_\{n,t\}m\_\{n,t\-1\}\\frac\{1\}\{\|\\mathcal\{O\}\|\}\\sum\_\{k\\in\\mathcal\{O\}\}\\left\|\\pi\_\{t,k\}^\{\(n\)\}\-\\pi\_\{t\-1,k\}^\{\(n\)\}\\right\|\}\{\\sum\_\{n,t\\geq 2\}m\_\{n,t\}m\_\{n,t\-1\}\}\.\(99\)The denominator is clamped to a positive value so that length\-one batches return a zero smoothness penalty rather than a division error\. Energy and delay proxy terms are optional:

ℒE=∑n,tmn,t​∑kπn,t,k​Ek∑n,tmn,t,ℒD=∑n,tmn,t​∑kπn,t,k​Dk∑n,tmn,t\.\\mathcal\{L\}\_\{E\}=\\frac\{\\sum\_\{n,t\}m\_\{n,t\}\\sum\_\{k\}\\pi\_\{n,t,k\}E\_\{k\}\}\{\\sum\_\{n,t\}m\_\{n,t\}\},\\qquad\\mathcal\{L\}\_\{D\}=\\frac\{\\sum\_\{n,t\}m\_\{n,t\}\\sum\_\{k\}\\pi\_\{n,t,k\}D\_\{k\}\}\{\\sum\_\{n,t\}m\_\{n,t\}\}\.\(100\)For spiking variants, spike\-rate regularization is

ℒZ=\|1Nm​H​∑n,t,imn,t​z¯n,t,i−ρtarget\|\.\\mathcal\{L\}\_\{Z\}=\\left\|\\frac\{1\}\{N\_\{m\}H\}\\sum\_\{n,t,i\}m\_\{n,t\}\\bar\{z\}\_\{n,t,i\}\-\\rho\_\{\\mathrm\{target\}\}\\right\|\.\(101\)Herez¯n,t,i\\bar\{z\}\_\{n,t,i\}is the micro\-step\-averaged spike activity returned for hidden unitiiat program steptt,HHis the number of spiking hidden units, andNm=∑n,tmn,tN\_\{m\}=\\sum\_\{n,t\}m\_\{n,t\}\. This absolute deviation defines the spike\-rate regularizer, which means that reported spike rates are therefore step\-level averages over internal micro\-steps, not raw micro\-step event counts\. Unless otherwise stated, the main 16\-wide runs use

λF=1,λT=0\.5,λG=1,λH=10−3,λS=10−3\.\\lambda\_\{F\}=1,\\quad\\lambda\_\{T\}=0\.5,\\quad\\lambda\_\{G\}=1,\\quad\\lambda\_\{H\}=10^\{\-3\},\\quad\\lambda\_\{S\}=10^\{\-3\}\.\(102\)

#### 2\.8\.10Training and evaluation protocol

The training procedure can be written without relying on implementation\-specific names:

1. 1\.Sample a mini\-batch of programs, initial registers, reference traces and masks\.
2. 2\.Encode each instruction intoϕt\\phi\_\{t\}and initialize the model state withr0r\_\{0\}and memoryM0M\_\{0\}\.
3. 3\.For each valid timestep, compute memory readqtq\_\{t\}, recurrent hidden statehth\_\{t\}, gate logitsℓt\\ell\_\{t\}, gate distributionπt\\pi\_\{t\}and candidateALUoutputsyt,ky\_\{t,k\}\.
4. 4\.Apply soft, Gumbel or hard gate selection according to the training/evaluation mode\.
5. 5\.Write the selected output to the destination register and update differentiable memory if enabled\.
6. 6\.Accumulate final, trace, gate, entropy, smoothness, energy, delay and spike penalties\.
7. 7\.Backpropagate through the unrolled computation graph\. For standardQAT8runs, quantization simulation of the selectedALUwriteback is active after the warmup schedule\. Therefore, for ValueMemory\-QAT8runs, the quantizedALUvalue is blended with the value\-memory read before the final clamp\.
8. 8\.At evaluation time, disable stochastic sampling, select hard deterministic gates and report final, trace, gate, calibration, robustness and proxy\-cost metrics\.

Every valid timestep therefore has both a register\-state target and a symbolic operation label\.

#### 2\.8\.11Benchmark taxonomy and comparative architecture interface

The benchmark suite is grouped into four task families\. The first family contains direct symbolic execution tasks such as randomALUprograms, add chains, sub chains and mixed arithmetic\. The second family contains algorithmic held\-out tasks such as parity, prefix sum, running maximum, reverse, small sort and function composition\. The third family contains memory\-pressure tasks such as delayed copy, associative lookup, pointer chasing and stack\-style reverse\. The fourth family contains equivalent\-program energy\-choice tasks such as redundant noop elimination, identity\-op skipping, low\-power shift\-add, memory\-copy minimum\-energy paths and micro\-op fusion\.

The sequence of task families increases mechanistic pressure\. Exact results on the first family establish the executor under direct visible\-opcode symbolic execution\. The later families test algorithmic generalization, delayed memory use and selection among equivalent symbolic paths with different proxy costs\. Degradation on these later families identifies where stronger memory and control mechanisms are required\.

These task families are evaluated using a controlled set of architecture variants rather than a collection of unrelated baselines\. The architectures share the same forward input/output interface:

modelθ​\(Xinstr,Xregs0,m\)↦\{r^T,r^1:T,ℓ1:T,π1:T,α1:Tread,α1:Twrite,z1:Toptional\}\.\\mathrm\{model\}\_\{\\theta\}\\\!\\left\(X\_\{\\mathrm\{instr\}\},X\_\{\\mathrm\{regs0\}\},m\\right\)\\mapsto\\left\\\{\\hat\{r\}\_\{T\},\\hat\{r\}\_\{1:T\},\\ell\_\{1:T\},\\pi\_\{1:T\},\\alpha^\{\\mathrm\{read\}\}\_\{1:T\},\\alpha^\{\\mathrm\{write\}\}\_\{1:T\},z\_\{1:T\}^\{\\mathrm\{optional\}\}\\right\\\}\.\(103\)
The model output contains the final register state, the complete register trace, gate logits, gate probabilities, memory read weights, memory write weights and optional spike traces\. Energy and delay are not predicted tensors returned by the model\. They are computed post hoc from operation labels, gate probabilities or spike traces using the proxy tables defined below\.

The shared output structure allows final\-state, trace, gate and memory\-access metrics to be computed consistently whenever the corresponding quantities are exposed by an architecture\. Every model is asked to solve the same symbolic execution problem under the applicable task\-family protocol\. Models without explicit operation gates leave gate\-path metrics unreported rather than being assigned an artificial gate interpretation\.

##### DCPU\-GRU\-NTM\.

The primary model combines instruction embeddings, a recurrent controller, differentiable memory, operation gates and masked register writes\. Its transition can be summarized as

qt\\displaystyle q\_\{t\}=Readθ​\(Mt−1,ht−1\),\\displaystyle=\\mathrm\{Read\}\_\{\\theta\}\(M\_\{t\-1\},h\_\{t\-1\}\),\(104\)ht\\displaystyle h\_\{t\}=GRUθ​\(\[ϕt;qt\],ht−1\),\\displaystyle=\\mathrm\{GRU\}\_\{\\theta\}\(\[\\phi\_\{t\};q\_\{t\}\],h\_\{t\-1\}\),\(105\)auxt\\displaystyle\\mathrm\{aux\}\_\{t\}=tanh⁡\(Waux​ht\+baux\),\\displaystyle=\\tanh\(W\_\{\\mathrm\{aux\}\}h\_\{t\}\+b\_\{\\mathrm\{aux\}\}\),\(106\)πt\\displaystyle\\pi\_\{t\}=Gateθ​\(\[rt−1,it;rt−1,jt;auxt;onehot​\(ot\)\]\),\\displaystyle=\\mathrm\{Gate\}\_\{\\theta\}\\\!\\left\(\[r\_\{t\-1,i\_\{t\}\};r\_\{t\-1,j\_\{t\}\};\\mathrm\{aux\}\_\{t\};\\mathrm\{onehot\}\(o\_\{t\}\)\]\\right\),\(107\)rt\\displaystyle r\_\{t\}=WriteReg​\(rt−1,πt,ht,xt\),\\displaystyle=\\mathrm\{WriteReg\}\(r\_\{t\-1\},\\pi\_\{t\},h\_\{t\},x\_\{t\}\),\(108\)Mt\\displaystyle M\_\{t\}=WriteMemθ​\(Mt−1,ht\)\.\\displaystyle=\\mathrm\{WriteMem\}\_\{\\theta\}\(M\_\{t\-1\},h\_\{t\}\)\.\(109\)The memory write in the primaryNTMpath is therefore controller\-state driven, since it does not directly consume the post\-ALUregister value\.

##### No\-gate\-loss ablation\.

The no\-gate\-loss ablation keeps the same architecture but setsλG=0\\lambda\_\{G\}=0\. It tests whether the explicit symbolic path matters\. If final loss stays low but gate accuracy and calibration collapse, the model has learned a less interpretable latent execution path\.

##### No\-memory ablation\.

The no\-memory model setsqt=0q\_\{t\}=0andMt=Mt−1M\_\{t\}=M\_\{t\-1\}for alltt\. Its transition is

ht=GRUθ​\(\[ϕt;0\],ht−1\)\.h\_\{t\}=\\mathrm\{GRU\}\_\{\\theta\}\(\[\\phi\_\{t\};0\],h\_\{t\-1\}\)\.\(110\)This ablation removes the explicit retrieved\-value channel\. On visible, local register tasks the recurrent state and instruction embedding can still carry enough context, but on delayed memory tasks the controller hidden state must now represent operation context, address history and retrieved value content simultaneously\. Degradation in this setting therefore identifies loss of addressable value retrieval, not a generic capacity difference\.

##### ValueMemory variant\.

The ValueMemory variant exposes an execution\-coupled value lane\. Read and write addresses are linear projections of controller state, and the read value can blend directly intoALUoperands and writeback:

αt=softmax​\(Wr​ht−1\),νt=∑iαt,i​Vt−1,i\.\\alpha\_\{t\}=\\mathrm\{softmax\}\(W\_\{r\}h\_\{t\-1\}\),\\qquad\\nu\_\{t\}=\\sum\_\{i\}\\alpha\_\{t,i\}V\_\{t\-1,i\}\.\(111\)Operand blending is

\[λu,λv\]=σ​\(Wλ​\[ht;νt\]\),uteff=ut\+λu​\(νt−ut\),vteff=vt\+λv​\(νt−vt\)\.\[\\lambda\_\{u\},\\lambda\_\{v\}\]=\\sigma\(W\_\{\\lambda\}\[h\_\{t\};\\nu\_\{t\}\]\),\\qquad u\_\{t\}^\{\\mathrm\{eff\}\}=u\_\{t\}\+\\lambda\_\{u\}\(\\nu\_\{t\}\-u\_\{t\}\),\\qquad v\_\{t\}^\{\\mathrm\{eff\}\}=v\_\{t\}\+\\lambda\_\{v\}\(\\nu\_\{t\}\-v\_\{t\}\)\.\(112\)AfterALUexecution, writeback blending and memory update are

y^t←clip​\(y^t\+λy​\(νt−y^t\),0,1\),Vt=Vt−1​\(1−ωt\)\+ωt​y^t,\\hat\{y\}\_\{t\}\\leftarrow\\mathrm\{clip\}\(\\hat\{y\}\_\{t\}\+\\lambda\_\{y\}\(\\nu\_\{t\}\-\\hat\{y\}\_\{t\}\),0,1\),\\qquad V\_\{t\}=V\_\{t\-1\}\(1\-\\omega\_\{t\}\)\+\\omega\_\{t\}\\hat\{y\}\_\{t\},\(113\)whereωt=softmax​\(Ww​ht\)\\omega\_\{t\}=\\mathrm\{softmax\}\(W\_\{w\}h\_\{t\}\)andλy=σ​\(Wy​\[ht;νt\]\)\\lambda\_\{y\}=\\sigma\(W\_\{y\}\[h\_\{t\};\\nu\_\{t\}\]\)\. This variant is motivated by hidden\-opcode memory\-pressure tasks, where delayed state can help execution\. When quantization simulation is enabled for ValueMemory variants, the quantizer is applied before the value\-memory writeback blend\. The subsequent blend is clamped but not re\-quantized\. ValueMemory\-QAT8results should therefore be read as quantized\-ALU/value\-memory robustness evaluations rather than strict final\-destination\-write quantization\.

##### Transformer\-NTM\.

The transformer controller replaces the recurrent update with causal self\-attention, producing a context vector that is then fused with theNTMread and the previous controller state through a shared projection:

H\\displaystyle H=Transformerθ​\(Φ\+P\),\\displaystyle=\\mathrm\{Transformer\}\_\{\\theta\}\(\\Phi\+P\),\(114\)qt\\displaystyle q\_\{t\}=Readθ​\(Mt−1,ht−1\),\\displaystyle=\\mathrm\{Read\}\_\{\\theta\}\(M\_\{t\-1\},h\_\{t\-1\}\),\(115\)ht\\displaystyle h\_\{t\}=tanh⁡\(Wstep​\[Ht;qt;ht−1\]\),\\displaystyle=\\tanh\\\!\\left\(W\_\{\\mathrm\{step\}\}\[H\_\{t\};\\,q\_\{t\};\\,h\_\{t\-1\}\]\\right\),\(116\)whereΦ\\Phiis the sequence of instruction/state embeddings andPPpositional encoding\. The attention outputHtH\_\{t\}is therefore an intermediate context, not the controller state used for gating andNTMwrites;hth\_\{t\}plays that role, matching how theGRU\-NTMprimary model separates a named mechanism from the sharedNTM\-coupled recurrence\. This construction can model long dependencies through attention but is less hardware\-friendly than the recurrent model because attention cost scales with sequence length\.

##### Transformer scratchpad\.

The scratchpad baseline receives the same instruction and initial\-register information but predicts the trace without explicit operation gates:

r^1:T=Decoderθ​\(Transformerθ​\(Xinstr,r0\)\)\.\\hat\{r\}\_\{1:T\}=\\mathrm\{Decoder\}\_\{\\theta\}\(\\mathrm\{Transformer\}\_\{\\theta\}\(X\_\{\\mathrm\{instr\}\},r\_\{0\}\)\)\.\(117\)It is included as an opaque trace\-prediction baseline\. It can report register errors, but because it has no gate trace it cannot support operation\-path metrics\.

##### TCN\-NTM\.

The temporal\-convolution controller uses dilated causal convolutions to produce a context vector, again fused with theNTMread and previous controller state through the shared projection:

ct\(ℓ\+1\)\\displaystyle c\_\{t\}^\{\(\\ell\+1\)\}=σ​\(∑j=0K−1Wℓ,j​ct−dℓ​j\(ℓ\)\+bℓ\),\\displaystyle=\\sigma\\left\(\\sum\_\{j=0\}^\{K\-1\}W\_\{\\ell,j\}c\_\{t\-d\_\{\\ell\}j\}^\{\(\\ell\)\}\+b\_\{\\ell\}\\right\),\(118\)qt\\displaystyle q\_\{t\}=Readθ​\(Mt−1,ht−1\),\\displaystyle=\\mathrm\{Read\}\_\{\\theta\}\(M\_\{t\-1\},h\_\{t\-1\}\),\(119\)ht\\displaystyle h\_\{t\}=tanh⁡\(Wstep​\[ct;qt;ht−1\]\),\\displaystyle=\\tanh\\\!\\left\(W\_\{\\mathrm\{step\}\}\[c\_\{t\};\\,q\_\{t\};\\,h\_\{t\-1\}\]\\right\),\(120\)wherectc\_\{t\}denotes the final\-layer TCN output at steptt\. The dilation schedule increases receptive field while keeping the model more parallel than aGRUand more local than a transformer; as with Transformer\-NTM,ctc\_\{t\}is an intermediate context andhth\_\{t\}is the controller state used for gating andNTMwrites\.

##### Graph\-DCPU\.

Despite its name, the implementedGraphDCPUBasecontroller is not a message\-passing graph neural network: it has no adjacency structure, no edge features and no neighbourhood aggregation\. At each step it embeds a fixed set of six feature blocks: \(i\) the instruction, \(ii\) the mean\-pooled register file, \(iii\) thesrca\\mathrm\{src\}\_\{a\}addressed\-register embedding, \(iv\) thesrcb\\mathrm\{src\}\_\{b\}addressed\-register embedding, \(v\) thedst\\mathrm\{dst\}addressed\-register embedding, and \(vi\) the pooledNTMread vector\. In addition, it fuses them through one shared two\-layerReLUMLP:

nt=tanh⁡\(MLPθ​\(\[ϕt;v¯t;vitt;vjtt;vdtt;qt\]\)\),n\_\{t\}=\\tanh\\\!\\left\(\\mathrm\{MLP\}\_\{\\theta\}\\\!\\left\(\\left\[\\phi\_\{t\};\\ \\bar\{v\}\_\{t\};\\ v\_\{i\_\{t\}\}^\{t\};\\ v\_\{j\_\{t\}\}^\{t\};\\ v\_\{d\_\{t\}\}^\{t\};\\ q\_\{t\}\\right\]\\right\)\\right\),\(121\)wherevrt=ReLU​\(Wreg​rt−1,r\+er\)v\_\{r\}^\{t\}=\\mathrm\{ReLU\}\(W\_\{\\mathrm\{reg\}\}r\_\{t\-1,r\}\+e\_\{r\}\)is a per\-register embedding with a learned register\-identity termere\_\{r\},v¯t\\bar\{v\}\_\{t\}is its mean over registers, andqtq\_\{t\}is theNTMread vector\. The non\-temporal variant usesht=nth\_\{t\}=n\_\{t\}directly\. This fixed six\-block fusion, not a relational graph over nodes and edges, is what the architecture name refers to in the current implementation\.

##### TemporalGraph\-DCPU\.

TemporalGraph\-DCPUadds a singleGRUCellacross timesteps on top of the same fused feature vector:

ht=GRUCellθ​\(nt,ht−1\)\.h\_\{t\}=\\mathrm\{GRUCell\}\_\{\\theta\}\(n\_\{t\},h\_\{t\-1\}\)\.\(122\)It is included as a comparison architecture controller variant to test whether an explicit register/operand feature fusion followed by lightweight recurrence is a useful alternative to the primaryGRUcontroller’s direct instruction/memory input, not as a genuine graph\-structured message\-passing model\.

##### SSM\-DCPU\.

The state\-space variant replaces recurrent gating with a lightweight diagonal update, whose output is likewise fused with theNTMread and previous controller state:

st\\displaystyle s\_\{t\}=δ⊙st−1\+\(1−δ\)⊙tanh⁡\(Win​ϕt\),\\displaystyle=\\delta\\odot s\_\{t\-1\}\+\(1\-\\delta\)\\odot\\tanh\(W\_\{\\mathrm\{in\}\}\\phi\_\{t\}\),\(123\)ct\\displaystyle c\_\{t\}=tanh⁡\(Wout​LayerNorm​\(st\)\),\\displaystyle=\\tanh\(W\_\{\\mathrm\{out\}\}\\mathrm\{LayerNorm\}\(s\_\{t\}\)\),\(124\)qt\\displaystyle q\_\{t\}=Readθ​\(Mt−1,ht−1\),\\displaystyle=\\mathrm\{Read\}\_\{\\theta\}\(M\_\{t\-1\},h\_\{t\-1\}\),\(125\)ht\\displaystyle h\_\{t\}=tanh⁡\(Wstep​\[ct;qt;ht−1\]\),\\displaystyle=\\tanh\\\!\\left\(W\_\{\\mathrm\{step\}\}\[c\_\{t\};\\,q\_\{t\};\\,h\_\{t\-1\}\]\\right\),\(126\)whereδ=σ​\(η\)\\delta=\\sigma\(\\eta\)is a learned per\-channel decay andctc\_\{t\}is the diagonal\-update output before fusion\. It is included to test efficient long\-sequence control as a future alternative to attention\.

#### 2\.8\.12Spiking controller derivation

The spiking models keep arithmetic and register writes non\-spiking and use spikes only for controller memory\. This is a crucial design decision\. The continuousALUbank is already the symbolic execution surface, therefore forcing the arithmetic itself to spike would make the model harder to train and less auditable\. The spiking controller receives a direct\-current encoding of the instruction and memory/value read:

dt=WI​\[ϕt;qt\]\+bI,k=1,…,K,d\_\{t\}=W\_\{I\}\[\\phi\_\{t\};q\_\{t\}\]\+b\_\{I\},\\qquad k=1,\\ldots,K,\(127\)whereKKis the number of micro\-steps per program step\. For LIF neurons,

ct,k\+1\\displaystyle c\_\{t,k\+1\}=αc​ct,k\+dt\+Wrec​zt,k,\\displaystyle=\\alpha\_\{c\}c\_\{t,k\}\+d\_\{t\}\+W\_\{\\mathrm\{rec\}\}z\_\{t,k\},\(128\)ut,k\+1raw\\displaystyle u\_\{t,k\+1\}^\{\\mathrm\{raw\}\}=αu​ut,k\+ct,k\+1,\\displaystyle=\\alpha\_\{u\}u\_\{t,k\}\+c\_\{t,k\+1\},\(129\)zt,k\+1\\displaystyle z\_\{t,k\+1\}=surrogate​\_​spike​\(ut,k\+1raw−θ\),\\displaystyle=\\mathrm\{surrogate\\\_spike\}\(u\_\{t,k\+1\}^\{\\mathrm\{raw\}\}\-\\theta\),\(130\)ut,k\+1\\displaystyle u\_\{t,k\+1\}=ut,k\+1raw​\(1−zt,k\+1\)\.\\displaystyle=u\_\{t,k\+1\}^\{\\mathrm\{raw\}\}\(1\-z\_\{t,k\+1\}\)\.\(131\)For adaptive LIF neurons,

θt,k\\displaystyle\\theta\_\{t,k\}=θ0\+β​at,k,\\displaystyle=\\theta\_\{0\}\+\\beta a\_\{t,k\},\(132\)at,k\+1\\displaystyle a\_\{t,k\+1\}=γ​at,k\+zt,k\+1\.\\displaystyle=\\gamma a\_\{t,k\}\+z\_\{t,k\+1\}\.\(133\)The spike train is summarized as

z¯t=1K​∑k=1Kzt,k,\\bar\{z\}\_\{t\}=\\frac\{1\}\{K\}\\sum\_\{k=1\}^\{K\}z\_\{t,k\},\(134\)and passed to the same symbolic readout heads used by the non\-spiking controller\. The spike operator emits a hard threshold in the forward pass and uses a fast\-sigmoid surrogate gradient in the backward pass:

z=surrogate​\_​spike​\(u−θ\)\.z=\\mathrm\{surrogate\\\_spike\}\(u\-\\theta\)\.\(135\)The model returns the spike train averaged over theKKmicro\-steps of each program step, rather than raw micro\-step event tensors\. The training metric therefore reports an averaged spike rate and a simple spike\-energy proxy:

z¯n,t,i=1K​∑k=1Kzn,t,k,i,ρspike=1Nactive​H​∑n,t,imn,t​z¯n,t,i,Espike,proxy=ρspike​H,\\bar\{z\}\_\{n,t,i\}=\\frac\{1\}\{K\}\\sum\_\{k=1\}^\{K\}z\_\{n,t,k,i\},\\qquad\\rho\_\{\\mathrm\{spike\}\}=\\frac\{1\}\{N\_\{\\mathrm\{active\}\}H\}\\sum\_\{n,t,i\}m\_\{n,t\}\\bar\{z\}\_\{n,t,i\},\\qquad E\_\{\\mathrm\{spike,proxy\}\}=\\rho\_\{\\mathrm\{spike\}\}H,\(136\)whereHHis the spiking hidden size\. Reported spike counts are sums of averaged spike traces over active program steps\. These are not raw micro\-step event counts\. The spike\-energy proxy is not a hardware event\-energy model: it does not include synaptic fan\-out, routing, memory access, membrane\-update cost, technology node, leakage or measured event energy\. Our work reports these as proxy quantities only, and future neuromorphic deployment must replace them with measured event energy\.

#### 2\.8\.13Energy and delay proxies

Energy and delay values in this manuscript are dimensionless simulation proxies, not physical measurements\. For a programx1:Tx\_\{1:T\}, proxy energy is

E​\(x1:T\)=∑t=1Tc​\(ot\)\+cmem​\(t\),E\(x\_\{1:T\}\)=\\sum\_\{t=1\}^\{T\}c\(o\_\{t\}\)\+c\_\{\\mathrm\{mem\}\}\(t\),\(137\)wherec​\(ot\)c\(o\_\{t\}\)is the operation\-dependent cost\. In sequence\-energy scoring, fixed read, write and memory\-attention costs are added for each active step\. In the optional training loss, only the gate\-probability\-weighted operation table is used\. The spike\-rate proxyρspike\\rho\_\{\\mathrm\{spike\}\}and spike\-energy proxyEspike,proxyE\_\{\\mathrm\{spike,proxy\}\}introduced below are reported as separate spiking\-controller diagnostics\. The implemented sequence\-energy scoring used for benchmark and energy\-choice scoring never adds a spike\-derived term toE​\(x1:T\)E\(x\_\{1:T\}\)\. The delay equation is expressed as:

Δ​\(x1:T\)=∑t=1Td​\(ot\)\.\\Delta\(x\_\{1:T\}\)=\\sum\_\{t=1\}^\{T\}d\(o\_\{t\}\)\.\(138\)The sequence delay is the sum of operation delays only\. The fixed sequence\-energy memory terms are architecture\-agnostic proxy charges and are not conditioned on whether a particular model variant disables memory or whether a baseline is scratchpad\-style\. The purpose is to test whether the learned executor can expose meaningful cost traces and choose lower\-cost equivalent symbolic paths\. The manuscript therefore avoids claiming measured power, physical energy or physical delay\. Where a voltage parameter appears in the simulator, it acts only as aV2V^\{2\}multiplier on synthetic operation costs, therefore no capacitance, frequency, switching\-probability, leakage, thermal or circuit model is implemented\.

#### 2\.8\.14Equivalent\-program energy\-choice tasks

The energy\-choice dataset extends each sample with canonical and alternative valid traces:

\(xcan,xalt,xmin,r0,rT,r1:Tcan,r1:T′alt,r1:T′′min,Ecan,Ealt,Emin\)\.\(x^\{\\mathrm\{can\}\},x^\{\\mathrm\{alt\}\},x^\{\\min\},r\_\{0\},r\_\{T\},r\_\{1:T\}^\{\\mathrm\{can\}\},r\_\{1:T^\{\\prime\}\}^\{\\mathrm\{alt\}\},r\_\{1:T^\{\\prime\\prime\}\}^\{\\min\},E^\{\\mathrm\{can\}\},E^\{\\mathrm\{alt\}\},E^\{\\min\}\)\.\(139\)The final state is shared:

𝒯​\(r0,xcan\)=𝒯​\(r0,xalt\)=𝒯​\(r0,xmin\)=rT\.\\mathcal\{T\}\(r\_\{0\},x^\{\\mathrm\{can\}\}\)=\\mathcal\{T\}\(r\_\{0\},x^\{\\mathrm\{alt\}\}\)=\\mathcal\{T\}\(r\_\{0\},x^\{\\min\}\)=r\_\{T\}\.\(140\)A model trained with target policyπtarget=min​\_​energy\\pi\_\{\\mathrm\{target\}\}=\\mathrm\{min\\\_energy\}receivesxminx^\{\\min\}and is scored by final correctness, canonical trace distance, alternative trace distance, minimum\-energy trace distance and any\-valid trace distance:

dany​\(r^1:T\)=min⁡\{d​\(r^1:T,r1:Tcan\),d​\(r^1:T,r1:T′alt\),d​\(r^1:T,r1:T′′min\)\}\.d\_\{\\mathrm\{any\}\}\(\\hat\{r\}\_\{1:T\}\)=\\min\\left\\\{d\(\\hat\{r\}\_\{1:T\},r\_\{1:T\}^\{\\mathrm\{can\}\}\),d\(\\hat\{r\}\_\{1:T\},r\_\{1:T^\{\\prime\}\}^\{\\mathrm\{alt\}\}\),d\(\\hat\{r\}\_\{1:T\},r\_\{1:T^\{\\prime\\prime\}\}^\{\\min\}\)\\right\\\}\.\(141\)The energy gaps are

Δ​Ecan=Eexec−Ecan,Δ​Emin=Eexec−Emin\.\\Delta E\_\{\\mathrm\{can\}\}=E^\{\\mathrm\{exec\}\}\-E^\{\\mathrm\{can\}\},\\qquad\\Delta E\_\{\\min\}=E^\{\\mathrm\{exec\}\}\-E^\{\\min\}\.\(142\)HereEexecE^\{\\mathrm\{exec\}\}is computed post hoc from the executed or selected symbolic path, and not a direct model output\. This turns energy from a passive reporting channel into an execution constraint\.

## 3Results

### 3\.1Register\-machine execution interface

TheSymbolic Neural CPUis constructed so that the quantities exposed by the model are the same quantities used to audit it\. These quantities include the input instruction, the selected operation gate, the source and destination registers, the masked writeback, the complete register trace, optional memory access and the low\-precision replay reference\. This differs from an unconstrained sequence modelfθ​\(x1:T,r0\)↦rTf\_\{\\theta\}\(x\_\{1:T\},r\_\{0\}\)\\mapsto r\_\{T\}, which can match a final state without exposing whether the intermediate computation followed the intended program\.[Figure˜1](https://arxiv.org/html/2607.10021#S3.F1)therefore defines the execution interface used throughout the investigation\. The architecture is not only a trainable mapping, but the measurement surface on which trace faithfulness, gate agreement, replay exactness and failure modes are evaluated\.

The schematic should be read with the following scope conventions\. Solid arrows indicate runtime information flow, whereas dashed green paths denote reference targets \(register trace, operation gates and final state\) which are used for supervision and evaluation, and not for extra runtime inputs\. The memory block denotes*alternative*optional variants such as the Neural Turing Machine \(NTM, slot\-addressed\) or ValueMemory \(value\-addressed\), both sharing the same execution interface\. At most one memory variant is active in a trained instance, and the principal executor uses theGRU\-NTMconfiguration\.QAT8denotes eight\-bit quantization\-simulated writeback at the register boundary, where selected register writes are projected onto an eight\-bit fixed\-point grid and evaluated against a matched fixed\-point replay, as shown in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d and Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)\. This procedure does not constitute full integer\-only inference\. The schematic label “16\-bit state each step” refers to the principal1616\-wide continuous register profile, withW=16W\{=\}16scalar lanes per register in\[0,1\]\[0,1\]\. It does not refer to bit\-accurate 16\-bit integer arithmetic\. State variables, instruction encoding, gate notation and metrics are defined in[section˜2](https://arxiv.org/html/2607.10021#S2)and TableLABEL:tab:notation\.

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure1.png)Figure 1:Training interface for trace\-supervised symbolic execution\.\(a\)Open\-loop training interface with the module schematic above and batched tensor unrolling below\. Encoded instructions drive a GRU controller and a gated fixed\-operation ALU bank\. Masked writeback produces a register trace supervised against the reference interpreter, with an optional memory pathway and optional QAT8 writeback\.\(b\)One reference\-executed program showing the opcode strip, the register\-trajectory heatmap averaged over theW=16W\{=\}16scalar lanes of each register, and the 11\-dimensional instruction encoding at a selected step\.At each program step, the executor receives an encoded instructionxtx\_\{t\}, reads two source registers, predicts an operation distribution, computes a candidate update through a named ALU bank and writes only the destination register\. The resulting transition is

r^t=Fθ​\(r^t−1,xt\),\\hat\{r\}\_\{t\}=F\_\{\\theta\}\(\\hat\{r\}\_\{t\-1\},x\_\{t\}\),\(143\)wherer^t\\hat\{r\}\_\{t\}is the predicted register file\. In practice,FθF\_\{\\theta\}is factorized into an instruction encoder, optional memory read, recurrent controller state, interpretable operation\-gate distribution and masked destination\-register write\. This factorization is the core architectural contribution where final\-state imitation, trace reconstruction and operation\-path audit become separable measurements rather than one entangled endpoint score\.

The operation choice is represented by a probability vector over named CPU\-like operations,

y^t=∑k∈𝒪πt,k​Ak​\(r^t−1,it,r^t−1,jt\),\\hat\{y\}\_\{t\}=\\sum\_\{k\\in\\mathcal\{O\}\}\\pi\_\{t,k\}A\_\{k\}\(\\hat\{r\}\_\{t\-1,i\_\{t\}\},\\hat\{r\}\_\{t\-1,j\_\{t\}\}\),\(144\)whereiti\_\{t\}andjtj\_\{t\}are zero\-based source\-register indices,AkA\_\{k\}is the implemented continuous operation bank andπt,k\\pi\_\{t,k\}is the learned gate probability\. The operation bank is not a bit\-accurate integer ISA\. It is a differentiable, bounded execution substrate whose operation identities remain visible\. Each transition therefore has a symbolic explanation, where which operation was selected, which operands were read and which register was written\.

The low\-precision behaviour is also made part of the interface rather than treated as a post\-hoc compression step\. When QAT8 is enabled, the selected writeback value is projected onto the same eight\-bit simulated quantization grid used by the matched fixed\-point replay,

QB​\(x\)=clip​\(round​\(x​\(2B−1\)\),0,2B−1\)2B−1\.Q\_\{B\}\(x\)=\\frac\{\\mathrm\{clip\}\(\\mathrm\{round\}\(x\(2^\{B\}\-1\)\),0,2^\{B\}\-1\)\}\{2^\{B\}\-1\}\.\(145\)HereBBdenotes the quantization bit depth only\. The matched replay is an independent fixed\-point reimplementation of the reference interpreter\. It is executed on the same programs at bit depthBBand never consults the model’s outputs\. Agreement with this replay is therefore an external verification of low\-precision execution semantics rather than a self\-consistency measure\. The implementation does not claim full integer\-only inference or measured hardware energy\.

The same interface supports variants without changing the audit surface\. The primaryGRU\-NTMexecutor uses slot\-addressed NTM memory\. The ValueMemory replaces the latter with value\-addressed memory for hidden\-opcode pressure tests, and spikingALIFcontrollers replace the recurrent controller state with event\-driven temporal state while leaving the symbolic ALU and writeback path non\-spiking\. The architecture ablations and scratchpad baselines consume the same instruction and register layout, which makes their failures interpretable\. Therefore, a baseline can match endpoints yet fail to expose the named operation path\.

Finally, equivalent\-program tasks turn cost from a passive label into a symbolic choice\. The benchmark constructs alternative programs that reach the same final state but have different dimensionless proxy costs, so the executor can be scored against a minimum\-energy symbolic path,

x⋆=arg​minx∈𝒳​\(r0,rT\)​E​\(x\)subject​to𝒯​\(r0,x\)=rT\.x^\{\\star\}=\\mathrm\{arg\\,min\}\_\{x\\in\\mathcal\{X\}\(r\_\{0\},r\_\{T\}\)\}E\(x\)\\quad\\mathrm\{subject\\ to\}\\quad\\mathcal\{T\}\(r\_\{0\},x\)=r\_\{T\}\.\(146\)Thus canonical\-path agreement is not always the appropriate metric\. A lower\-cost program can be correct when it follows a different valid trace\. These distinctions organize the Results\. The main evidence is trace\-verified visible\-opcode execution with matched replay, where the next evidence identifies mechanisms and limits through ablations, perturbations, cost choice and hidden\-opcode memory pressure\. The final sections extend the same interface to rollout diagnostics, spiking controllers, closed\-loop control and RV32I base\-integer semantics\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)evaluates whether the architecture preserves long\-horizon execution under hard gates and QAT8 writeback\.[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)then changes the evaluation of the perturbation input condition, equivalent program cost, architecture class or hidden\-opcode memory pressure to identify which component of the execution stack is challenged\. Finally,[figs\.˜4](https://arxiv.org/html/2607.10021#S3.F4),[5](https://arxiv.org/html/2607.10021#S3.F5)and[6](https://arxiv.org/html/2607.10021#S3.F6)inspect the same execution interface at rollout level, where selected non\-spiking executions, spiking\-controller dynamics and closed\-loop candidate\-constrained instruction selection\. The detailed tensor shapes, loss definitions, generation protocols and controller objectives are given in Methods\.

### 3\.2Length\-stableQAT8execution on visible\-opcode programs

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure2.png)Figure 2:Symbolic\-execution benchmark envelope on the 16\-wide register\-machine profile\.Panels show continuous\-reference hard\-execution error, QAT8 faithfulness, gate calibration, matched fixed\-point replay recovery and within\-program trace\-error localization\. The 32\-wide extrapolation profile is overlaid in panels \(a–c\); detailed metric, replay, uncertainty and proxy\-cost conventions are given in the surrounding text\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)establishes the main execution result before relaxing the assumptions of the benchmark\. The experiment follows the principal 16\-wide visible\-opcode register profile \(W=16W\{=\}16\) from short programs toL=1000L\{=\}1000under deterministic hard execution, and separates five quantities that would otherwise be a conflated and continuous\-reference register error, symbolic\-path faithfulness, gate calibration, matched fixed\-point replay and the location of error within a program\. This separation matters because a small continuous drift, a wrong opcode path and a reference\-semantics mismatch are different scientific outcomes\. A low\-precision executor should therefore not be judged only by its terminal state\.

All trained families in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)are evaluated with hard argmax gates, evaluation temperatureτ=0\.5\\tau\{=\}0\.5for the stored gate probabilities, continuous\-reference scoring unless replay is stated explicitly, and 8 benchmark batches of 64 synthetic programs per length \(512 programs per length point, evaluation seed 321\)\. The length grid combines a core sweep,L∈\{20,30,40,60,80,100,140,200,260,320,400,500\}L\\in\\\{20,30,40,60,80,100,140,200,260,320,400,500\\\}, with a long\-horizon extension,L∈\{600,700,800,900,1000\}L\\in\\\{600,700,800,900,1000\\\}\. Curves aggregate batch means\. Error bars combine within\-batch standard deviation and across\-instance spread when a plotted family contains multiple trained instances\. Exact metric definitions \(MAE, faithfulness,ECE\\mathrm\{ECE\},Brier\\mathrm\{Brier\}, proxy energy and proxy delay\) are given in Methods\.

The comparison has three primary families\. Thenon\-QAT exactGRU\-NTMexecutor omits quantization simulation and defines the continuous\-reference ceiling\. Hard final and trace errors are effectively zero and are drawn at the10−710^\{\-7\}display floor on log axes\. TheQAT8 familypools four eight\-bit quantization\-simulated writeback trained instances with the same architecture but different seed or warmup schedule\. The warmup condition trains briefly in full precision before enabling 8\-bit writeback simulation\. Thelong\-program ValueMemory QAT8profile is aQAT8GRU\-ValueMemory instance trained under a longer\-program, memory\-augmented regime to test deployment\-facing extrapolation\. This condition denotes a training and data regime rather than a hardware result\. No device\-specific timing, bandwidth or power model is applied\.

A widerW=32W\{=\}32profile is overlaid in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)a to c only as a secondary extrapolation envelope\. This trained instance saw programs no longer than 40 steps during training and was then evaluated far beyond that horizon\. Its long\-horizon limit is therefore not interpreted as a state\-width capacity limit\. Retraining the same architecture at a longer horizon removes the limit \(Supplementary Fig\.[S16](https://arxiv.org/html/2607.10021#Sx1.F16)and Table[S1](https://arxiv.org/html/2607.10021#Sx1.T1)\)\. The complete 32\-wide length\-resolved analysis, including faithfulness, calibration and per\-operation structure, is kept in Supplementary Figs\.[S1](https://arxiv.org/html/2607.10021#Sx1.F1)and[S2](https://arxiv.org/html/2607.10021#Sx1.F2)as our main analysis remains centred on the robust 16\-wide profile\.

The figure separates complementary failure modes, including length stability under hard execution, preservation of the named operation path, calibration of the soft gate probabilities, scoring against matched low\-precision semantics, and the location of residual error within a program \([fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)a to e\)\. The central result is thatQAT8decouples discrete logical correctness from continuous numerical matching\. Operation paths stay effectively exact throughL=1000L\{=\}1000while continuous\-reference register MAE remains in the10−310^\{\-3\}band\.

We first assess performance and logical reliability\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)a plots*mean absolute error*\(MAE\\mathrm\{MAE\}\) between hard\-executed register files and the*continuous*reference on a log scale versus program length\.Final MAEcompares terminal statesr^T\\hat\{r\}\_\{T\}vs\.rTrefr\_\{T\}^\{\\mathrm\{ref\}\}\.Trace MAEaverages over active timesteps and register lanes \(maskedℓ1\\ell\_\{1\}norm as in training,[section˜2](https://arxiv.org/html/2607.10021#S2)\)\. The solid lines are final error and dashed lines are trace error\.non\-QAT exacthard execution is numerically exact against the continuous reference \(final MAE effectively0at all reported lengths, including the longest testedL=1000L\{=\}1000\)\. Because theyy\-axis is logarithmic, these zero values are drawn at a10−710^\{\-7\}display floor, so the flat bottom line marks exactness rather than a small nonzero error\. TheQAT8 familyandlong\-program ValueMemory QAT8curves lie orders of magnitude above that floor yet remain bounded across the full horizon\. PrimaryQAT8hard final MAE is2\.01×10−3±3\.8×10−42\.01\\times 10^\{\-3\}\\pm 3\.8\\times 10^\{\-4\}atL=30L\{=\}30, peaks at4\.35×10−3±1\.8×10−34\.35\\times 10^\{\-3\}\\pm 1\.8\\times 10^\{\-3\}atL=100L\{=\}100, remains elevated at3\.83×10−3±7\.8×10−43\.83\\times 10^\{\-3\}\\pm 7\.8\\times 10^\{\-4\}atL=200L\{=\}200, and eases toward the range from2×10−32\\times 10^\{\-3\}to2\.5×10−32\.5\\times 10^\{\-3\}by longer horizons \(2\.28×10−3±6\.7×10−42\.28\\times 10^\{\-3\}\\pm 6\.7\\times 10^\{\-4\}atL=500L\{=\}500,2\.46×10−3±4\.4×10−42\.46\\times 10^\{\-3\}\\pm 4\.4\\times 10^\{\-4\}atL=1000L\{=\}1000, Table[1](https://arxiv.org/html/2607.10021#S3.T1)\)\. Pooling the four 16\-wideQAT8trained instances over all benchmark lengths and batches, the aggregated family finalMAE\\mathrm\{MAE\}is2\.87×10−32\.87\\times 10^\{\-3\}\(95%95\\%bootstrap confidence interval\[2\.76,2\.99\]×10−3\[2\.76,2\.99\]\\times 10^\{\-3\},n=544n\{=\}544per\-length, per\-batch samples\)\. Trace MAE follows a similar pattern \(1\.14×10−31\.14\\times 10^\{\-3\}atL=30L\{=\}30,2\.83×10−32\.83\\times 10^\{\-3\}atL=100L\{=\}100,4\.54×10−34\.54\\times 10^\{\-3\}atL=200L\{=\}200,2\.86×10−32\.86\\times 10^\{\-3\}atL=500L\{=\}500, and2\.64×10−32\.64\\times 10^\{\-3\}atL=1000L\{=\}1000\)\. The long\-program ValueMemoryQAT8profile tracks the primary within∼1%\{\\sim\}1\\%at representative lengths throughL=1000L\{=\}1000\. For inspectable symbolic execution, the critical threshold is not bit\-exact floating\-point agreement with a continuous reference but*opcode routing and trace inspectability*under quantization\-simulated writeback\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)b shows that althoughQAT8exhibits higher continuous\-reference MAE than non\-QAT8exact, this numerical noise does not corrupt logical routing\.Gate path\(gate agreement,AGA\_\{G\}in[section˜2](https://arxiv.org/html/2607.10021#S2)\) is the fraction of active steps where the hard\-selected operationo^t=arg⁡maxk⁡ℓt,k\\hat\{o\}\_\{t\}=\\arg\\max\_\{k\}\\ell\_\{t,k\}\(the operation with the largest gate logit,[eq\.˜10](https://arxiv.org/html/2607.10021#S2.E10)\) equals the reference opcode \(the operation the reference interpreter executed at that step\)\. For the aggregated family it remains100\.0%at every length throughL=700L\{=\}700and stays at or above98\.7%\\mathbf\{98\.7\\%\}throughL=1000L\{=\}1000, with the primary and long\-program ValueMemory trained instances individually holding100\.0%100\.0\\%at every length toL=1000L\{=\}1000\(the small aggregate dip atL≥800L\\geq 800comes from two seed replicates,n=32n\{=\}32batch records per length across fourQAT8trained instances\)\.

This measurement isolates the main execution claim\. The neural controller selects the correct named operation at essentially every step even at long extrapolation lengths, when register values drift in continuous space\.Tolerance10−210^\{\-2\}measures a softer register criterion \(the fraction of programs with‖r^T−rTref‖∞≤10−2\\\|\\hat\{r\}\_\{T\}\-r\_\{T\}^\{\\mathrm\{ref\}\}\\\|\_\{\\infty\}\\leq 10^\{\-2\}in normalized\[0,1\]\[0,1\]space\) and stays in the range from𝟓𝟔%\\mathbf\{56\\%\}to𝟕𝟒%\\mathbf\{74\\%\}\(dropping to56\.3%\\mathbf\{56\.3\\%\}atL=200L\{=\}200,71\.1%\\mathbf\{71\.1\\%\}atL=500L\{=\}500and69\.9%\\mathbf\{69\.9\\%\}atL=1000L\{=\}1000\)\. That tolerance dip co\-varies with the MAE peak at lengths fromL≈100L\{\\approx\}100toL=200L\{=\}200while gate agreement remains exact, explicitly decoupling continuous numerical looseness from opcode faithfulness\.Scalar\-grid exactis stricter still\. Each scalar lane must match the reference after projecting both sides onto the profile\-dependent fixed\-point grid \(not packed machine\-word equality\)\. It stays in the range from𝟐𝟑%\\mathbf\{23\\%\}to𝟒𝟏%\\mathbf\{41\\%\}against the*continuous*reference \(the strictest lower bound before matched replay scoring\)\. Continuous\-reference MAE therefore measures reference\-semantics mismatch under 8\-bit writeback, not gate collapse\. Matched fixed\-point replay yields 100% scalar\-grid faithfulness \([fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d, Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7), Table[2](https://arxiv.org/html/2607.10021#S3.T2)\)\.

Calibration provides a complementary view of gate trustworthiness\. Deterministic hard execution is assessed as an opcode decision problem through gate agreement, whereas probability calibration is meaningful for the soft gate distribution before argmax selection\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)c therefore reportssoft\-modediagnostics\. Expected calibration error \(ECE\\mathrm\{ECE\}\) and Brier score \(Brier\\mathrm\{Brier\}\) between predicted gate probabilities and reference opcode labels\[[17](https://arxiv.org/html/2607.10021#bib.bib25),[6](https://arxiv.org/html/2607.10021#bib.bib26)\]are averaged over all length and batch records in each family and displayed as−log10⁡\(error\)\-\\log\_\{10\}\(\\mathrm\{error\}\)\(higher is better\)\. These scores use the model’s raw predicted gate probabilities directly\. No post\-hoc temperature scaling or Platt recalibration is applied before computingECE\\mathrm\{ECE\}orBrier\\mathrm\{Brier\}, so they reflect the executor’s native confidence rather than a recalibrated proxy\. These metrics expose residual probability mass when gates are evaluated in soft form during benchmarking, not a contradiction with exact hard routing\. Evaluated across the full range fromL=20L\{=\}20toL=1000L\{=\}1000\(deep extrapolation included\), soft errors are larger and more variable than within the core sweep\. Thenon\-QAT exactmean softECE\\mathrm\{ECE\}is2\.0×10−32\.0\\times 10^\{\-3\}\(−log10⁡ECE≈2\.7\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 2\.7\) and itsBrier\\mathrm\{Brier\}score is4\.0×10−34\.0\\times 10^\{\-3\}\(−log10⁡Brier≈2\.4\-\\log\_\{10\}\\mathrm\{Brier\}\\approx 2\.4\)\. TheQAT8 familymean softECE\\mathrm\{ECE\}is9\.0×10−49\.0\\times 10^\{\-4\}\(−log10⁡ECE≈3\.0\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 3\.0\) and itsBrier\\mathrm\{Brier\}score is1\.5×10−31\.5\\times 10^\{\-3\}\(−log10⁡Brier≈2\.8\-\\log\_\{10\}\\mathrm\{Brier\}\\approx 2\.8\)\. These soft errors are dominated by the long extrapolation lengths and, within theQAT8family, by the warmup instance \(softECE\\mathrm\{ECE\}3\.4×10−33\.4\\times 10^\{\-3\}\)\. The primaryQAT8instance alone remains an order of magnitude better \(softECE\\mathrm\{ECE\}3\.2×10−53\.2\\times 10^\{\-5\},−log10⁡ECE≈4\.5\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 4\.5\)\. These are*soft*\-mode residuals only\. Hard argmax routing is summarized separately by gate agreement, so the soft drift reflects less\-peaked gate probability mass at long horizons rather than necessarily erroneous opcode routing\. Visual scatter in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)c largely reflects within\-family spread across the fourQAT8trained instances \(the warmup instance being the least soft\-calibrated\) and the compression of errors spanning from10−310^\{\-3\}to10−1410^\{\-14\}on a−log10\-\\log\_\{10\}axis, not competing statistical verdicts\.Long\-program ValueMemory QAT8shows the best soft calibration \(−log10⁡ECE≈7\.7\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 7\.7,−log10⁡Brier≈13\.7\-\\log\_\{10\}\\mathrm\{Brier\}\\approx 13\.7\) despite MAE similar to primaryQAT8, indicating that calibration is sensitive to the training regime and initialization rather than to continuous\-reference MAE alone\. BothECE\\mathrm\{ECE\}andBrier\\mathrm\{Brier\}are included to avoid relying on a single calibration metric\. Extended calibration curves appear in the supplementary execution diagnostics\.

Proxy cost is not the axis that separates these families\. A natural concern is whether proxy cost confounds the accuracy interpretation in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)a to c\. It does not, because under the shared proxy formula the standard length benchmark assigns nearly identical per\-step operation costs to the compared families\. The comparison uses dimensionless simulation proxies for operation\-level energy and delay \([section˜2](https://arxiv.org/html/2607.10021#S2)\),*not*measured silicon power or cycle\-accurate timing\. Per\-family proxy totals are divided by program lengthLL, then normalized to the meanQAT8primary per\-step values\. Acrossnon\-QAT exact,QAT8 family, andlong\-program ValueMemory QAT8, per\-step energy and delay cluster within the range from0\.995\\mathbf\{0\.995\}to1\.005\\mathbf\{1\.005\}of theQAT8reference, and are width\-independent by construction because all families and profiles share the same proxy ISA formula\. Trained\-instance or width choice does not artificially inflate or deflate cost in the simulator\. Per\-step normalization therefore rules out a proxy\-cost artefact\. The primaryQAT8proxy energy grows approximately linearly with length \(≈8059\\approx 8059atL=200L\{=\}200,≈20150\\approx 20150atL=500L\{=\}500and≈40297\\approx 40297atL=1000L\{=\}1000\), but the compared families are not separated by this axis \(Table[3](https://arxiv.org/html/2607.10021#S3.T3)and supplementary proxy\-cost diagnostics\)\. Proxy cost becomes scientifically relevant only when the program itself is allowed to change\. Equivalent\-program energy\-choice tasks are therefore analysed later \([fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)b and Table[5](https://arxiv.org/html/2607.10021#S3.T5)\), where lower\-cost valid traces are competing execution paths rather than post\-hoc labels attached to one path\.

The analysis then moves from continuous scoring to replay semantics\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)is an open\-loop length benchmark scored first against the continuous reference transition\. In that reference frame, theQAT8family trades floating\-point precision for length\-stable symbolic execution\. Final\-state drift stays in the range from∼2×10−3\{\\sim\}2\\times 10^\{\-3\}to2\.5×10−32\.5\\times 10^\{\-3\}at long horizons, gate paths remain effectively exact, and the drift is an order of magnitude below the10−210^\{\-2\}final\-state tolerance used for downstream closed\-loop success \([section˜3\.11](https://arxiv.org/html/2607.10021#S3.SS11)\)\. The appropriate hardware\-facing question is then whether this drift persists when the reference is changed to the same low\-precision semantics as the model\. The matched fixed\-point replay in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d and Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)answers that question\. On the task\-split device\-reference evaluations of the primaryQAT8executor \([table˜2](https://arxiv.org/html/2607.10021#S3.T2)\), final and trace MAE are zero and scalar\-grid faithfulness is 100% under the same eight\-bit writeback semantics the executor was trained to satisfy\. The evidence remains simulation\-level\. It does not establish measured silicon energy, cycle\-accurate timing, full integer\-only inference or a complete instruction\-set emulator\. The supported claim is semantics\-preserving quantization\-simulated writeback with an inspectable opcode trace\.

[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)summarizes the symbolic\-execution benchmark envelope on the principal 16\-wide register\-machine profile \([section˜3\.2](https://arxiv.org/html/2607.10021#S3.SS2)\)\. Metric formulas are defined in[section˜2\.3](https://arxiv.org/html/2607.10021#S2.SS3), and symbols are summarized in TableLABEL:tab:notation\. The profile label denotes register*width*in continuous state variables,*not*bit\-accurate integer arithmetic\. “16\-wide” is the principal1616\-state\-variable profile and is unrelated to a 16\-bit instruction\-set architecture \(ISA\)\.

A wider3232\-state\-variable*extrapolation*profile, shown in sage green and drawn semi\-transparently, is overlaid as a secondary envelope in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)a to c\. This profile comes from a trained instance exposed only to programs of at most 40 instructions during training, and is included to probe extrapolation far past its training horizon\. Its long\-horizon limit is a training\-horizon effect, not a state\-width limit \(Supplementary Fig\.[S16](https://arxiv.org/html/2607.10021#Sx1.F16)\)\. Its full length\-resolved breakdown is reported separately in Supplementary Figs\.[S1](https://arxiv.org/html/2607.10021#Sx1.F1)and[S2](https://arxiv.org/html/2607.10021#Sx1.F2)\.

The legend names three trained\-instance families\.non\-QAT8exactdenotes the non\-quantized hard\-execution continuous\-reference ceiling\.QAT8familydenotes four eight\-bit quantization\-simulated writeback instances that differ in seed or warmup\.long\-program ValueMemoryQAT8denotes the extended value\-memory long\-program variant\.

[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)a reports hard final and trace mean absolute error \(MAE\\mathrm\{MAE\}\) as a function of program length, fromL=20L\{=\}20toL=1000L\{=\}1000, whereLLis the number of executed instructions\. Solid curves are final\-state errors and dashed curves are trace errors, both measured against the continuous\-reference trajectory and plotted on a logarithmic scale\. Matched\-replay recovery is summarized in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d\. FinalMAE\\mathrm\{MAE\}measures endpoint imitation, whereas traceMAE\\mathrm\{MAE\}measures whether the whole trajectory is preserved\. The non\-QAT8exact baseline is numerically exact at every length, with finalMAE\\mathrm\{MAE\}equal to0and drawn at a10−710^\{\-7\}display floor only for log\-axis visibility\. It establishes the continuous\-reference ceiling against which theQAT8families are scored\. The semi\-transparent sage\-green*32\-wide extrapolation*curves, with final error solid and trace error dashed, trace the short\-horizon\-trained extrapolation profile\. It is numerically exact at the10−710^\{\-7\}floor throughL≈400L\{\\approx\}400, then shows a sharp long\-horizon divergence rising to between∼4×10−2\{\\sim\}4\\times 10^\{\-2\}and5×10−25\\times 10^\{\-2\}byL=1000L\{=\}1000, in contrast to the length\-stable 16\-wide families\. This overlaid3232\-state\-variable profile is exact at short lengths and exhibits a clear long\-horizon extrapolation boundary\. Its multi\-seed length\-resolved breakdown, including faithfulness, calibration and per\-operation structure, is detailed in Supplementary Figs\.[S1](https://arxiv.org/html/2607.10021#Sx1.F1)and[S2](https://arxiv.org/html/2607.10021#Sx1.F2)\. Error bars combine benchmark\-batch standard deviation and across\-instance spread within each family, not cross\-seed uncertainty for single\-instance families\. Formal95%95\\%bootstrap confidence intervals and the significance tests quoted in the main text \([section˜2](https://arxiv.org/html/2607.10021#S2)\) are computed from the pooled per\-length, per\-batch samples\.

[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)b reports faithfulness on the aggregatedQAT8family\. The*gate path*is the fraction of active steps with the correct hard argmax opcode relative to the reference interpreter\. It is saturated through the core horizon and remains near\-saturated at the longest lengths\.*Tolerance10−210^\{\-2\}*is the fraction of programs whose final\-stateℓ∞\\ell\_\{\\infty\}error is at most10−210^\{\-2\}\.*Scalar\-grid exact*is agreement after projecting register components onto the fixed\-point grid, and should not be read as packed\-word bit equality\. All three quantities are measured against the continuous reference interpreter\. The semi\-transparent sage\-green*32\-wide scalar\-grid*curve overlays the same short\-horizon\-trained extrapolation profile\. It is exact, approximately100%100\\%, throughL≈400L\{\\approx\}400, then declines to between∼88%\{\\sim\}88\\%and90%90\\%at long horizons, consistent with Supplementary Fig\.[S2](https://arxiv.org/html/2607.10021#Sx1.F2)c\.

[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)c reports gate calibration over operation\-gate predictions for the three 16\-wide families \(non\-QAT8exact,QAT8, and long\-program ValueMemoryQAT8\) together with the overlaid 32\-wide extrapolation profile\. Soft\-mode expected calibration error \(ECE\\mathrm\{ECE\}\) and theBrier\\mathrm\{Brier\}score are distinct metrics, and both are plotted as−log10⁡\(error\)\-\\log\_\{10\}\(\\mathrm\{error\}\), so higher values are better\. Hard argmax routing is reported as gate agreement in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)b and is not interpreted as probability calibration\. Within each row, faint points and the connecting bar show the score distribution, and the large marker shows its mean\. For the three 16\-wide rows, this spread is taken*across seeds/runs*at matched length aggregation\. For the single\-run*32\-wide extrapolation*row, the spread is taken*across program lengths*\. Its wide range therefore reflects calibration that is tight at short programs but degrades steeply toward the long\-horizon limit, rather than seed\-to\-seed variability\.

[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)d reports faithfulness recovered by matched fixed\-point replay across five evaluation splits, combining seen versus held\-out task families with seen versus held\-out program lengths as defined in[section˜2](https://arxiv.org/html/2607.10021#S2)\. The panel compares continuous\-reference tolerance faithfulness, shown in orange, with exact matched\-replay faithfulness, shown as green diamonds, and annotations give the recovered percentage points, from\+7\+7to\+48\+48, with the largest recovery on held\-out tasks*and*held\-out lengths\. Matched replay is an independent fixed\-point reimplementation of the reference instruction set executed at the model’s 8\-bit writeback precision\. It is not the model grading its own rounding, and it is an*offline scoring/verification reference computed after execution, not a runtime fallback*\. The neural executor remains the object being evaluated, and only its register writeback is quantization\-simulated rather than full integer\-only inference\. The full split\-level breakdown is reported in Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)and Table[2](https://arxiv.org/html/2607.10021#S3.T2)\.[Figure˜2](https://arxiv.org/html/2607.10021#S3.F2)e localizes execution error within each program\. It shows per\-step hard traceMAE\\mathrm\{MAE\}on alog10\\log\_\{10\}scale, with a shared colour bar, as a heatmap over normalized execution progress, step/\(L−1\)/\(L\{\-\}1\), on the horizontal axis and program length on the vertical axis\. The left heatmap shows the 16\-wideQAT8family, and the right heatmap shows the 32\-wide extrapolation profile\. The 16\-wide plateau is reached within the first∼10%\{\\sim\}10\\%of execution and is essentially length\-independent\. The 32\-wide high\-error boundary is diagonal because error onset occurs at a fixed absolute step,≈494\{\\approx\}494, corresponding to normalized progress494/L494/L\. The full diagnostic is shown in Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)\.

Per\-step energy and delay proxy cost is omitted from the main benchmark panel because it is width\- and family\-agnostic under the shared proxy formula\. The cost\-choice experiment where proxy cost changes the executed path appears in[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)b\.

Table 1:PrimaryQAT8length benchmark under hard deterministic execution and the continuous reference\.Means±\\pmbenchmark\-batch standard deviation over the benchmark batches at each length \(4 batches forL≤200L\\leq 200from the original benchmark bundle; 8 batches forL≥500L\\geq 500from the long\-horizon grid\)\. Full curves are shown in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)a,b\. AtL=500L\{=\}500, gate agreement remains 1\.000 and tolerance faithfulness is 0\.711 under the continuous reference\. AtL=1000L\{=\}1000, gate agreement remains 1\.000, tolerance faithfulness is 0\.699 and final MAE is2\.46×10−32\.46\\times 10^\{\-3\}\. Matched replay is exact, as shown in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d and Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)\. The long\-horizon rows extend the same evaluation protocol toL=500L\{=\}500andL=1000L\{=\}1000\.
### 3\.3Matched replay separates reference drift from execution error

The continuous reference used in the length benchmark is the right ceiling for a non\-quantized executor, but it is not the only meaningful reference for a model that is constrained to eight\-bit writeback\. In the implemented metrics, “exact” low\-precision faithfulness is computed by projecting continuous register\-vector components onto the profile\-dependent scalar grid\. It is not equality of packed machine\-word bits\.

The matched fixed\-point replay provides the corresponding low\-precision reference\. It is an independent reimplementation of the reference instruction set, executed on the same programs at the model’s 8\-bit writeback precision\. It does not consult the model’s outputs and is not a runtime fallback\. The neural executor remains the object being evaluated, while the replay defines the correct eight\-bit trajectory for that program\.

Under this matched reference, every tested split has zero replay final MAE, zero replay trace MAE, 100% exact scalar\-grid faithfulness and gate agreement of 1\.000\. These saturated matched\-replay quantities are stated in the text rather than repeated in every row of Table[2](https://arxiv.org/html/2607.10021#S3.T2)\. The table therefore reports the continuous\-reference MAE, which is the quantity that varies across the evaluation splits \([fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d and Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)\)\.

The recovery is largest exactly where continuous scoring is most pessimistic\. Tolerance faithfulness that falls to70%70\\%on held\-out tasks and52%52\\%on held\-out tasks*and*lengths returns to100%100\\%under matched replay\. These changes correspond to gains of\+30\+30and\+48\+48percentage points \([fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d and Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)c\)\. Final and trace MAE also collapse to the numerical floor on every split, as shown in Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)b,d\. The continuous\-reference drift in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)a is therefore a reference\-semantics mismatch, not a failure of the quantization\-simulated replay\.

Table 2:Continuous\-reference error across matched fixed\-pointQAT8replay splits\.Matched replay gives zero final MAE, zero trace MAE, 100% exact scalar\-grid faithfulness and gate agreement of 1\.000 on every listed split\.
### 3\.4Long\-horizon quantization\-simulated writeback extrapolation

The replay result motivates a stricter extrapolation check\. If the low\-precision executor is following the intended symbolic path, increasing the number of executed instructions should not accumulate unbounded writeback error\. In an extended 16\-wideQAT8value\-memory benchmark at lengths 100, 200, 400 and 800, hard finalMAE\\mathrm\{MAE\}remained low\. The reported values were1\.20×10−41\.20\\times 10^\{\-4\}atL=100L=100,6\.38×10−56\.38\\times 10^\{\-5\}atL=200L=200,7\.12×10−57\.12\\times 10^\{\-5\}atL=400L=400and2\.99×10−52\.99\\times 10^\{\-5\}atL=800L=800, with hard gate agreement 1\.0 at all lengths\. The proxy energy increased approximately linearly with length, from 4028 atL=100L=100to 32245 atL=800L=800, as expected for a per\-instruction simulation cost\. These results support length scalability of the implemented symbolic execution substrate, while still being limited to the synthetic program families used in this study\.

Table 3:Extended long\-horizonQAT8value\-memory profile\.Energy and delay are simulation proxies\.The main experimental target remains the 16\-wide profile withQAT8writeback, because that setting provides the strongest low\-precision evidence under the available evaluation budget\. A separate 32\-wide profile probes whether the same implementation can handle larger continuous state vectors before moving toward realistic processor semantics\. Over the same short\-length range used for the 16\-wide profile, the 32\-wide extrapolation trained instance has hard finalMAE\\mathrm\{MAE\}0\.0 at lengths 40, 80 and 120, with gate agreement 1\.0\. This supports state\-width scalability for the implemented continuous symbolic reference interpreter, but it should not be read as emulation of a full 32\-bit instruction\-set architecture\. The remaining transition to processor realism requires typed immediates, branches, memory alignment, exceptions and system\-level state\.

Table 4:Supplementary 32\-wide extrapolation profile: short\-length range\.The result supports state\-width scalability under controlled symbolic tasks\.The same 32\-wide non\-QAT8trained instance reveals its limit only when the short\-length grid is extended to long horizons \(three evaluation seeds with eight benchmark batches each atL∈\{400,…,1000\}L\\in\\\{400,\\dots,1000\\\}, Supplementary Fig\.[S1](https://arxiv.org/html/2607.10021#Sx1.F1)\)\. Execution is numerically exact throughL=400L\{=\}400\. The first deviation appears atL=500L\{=\}500and is confined to the endpoint \(finalMAE\\mathrm\{MAE\}2\.0×10−32\.0\\times 10^\{\-3\}with traceMAE\\mathrm\{MAE\}still at the∼2×10−5\{\\sim\}2\\times 10^\{\-5\}floor\)\. Beyond this onset the error grows rather than recovering\. FinalMAE\\mathrm\{MAE\}rises roughly an order of magnitude intoL=600L\{=\}600\(2\.1×10−22\.1\\times 10^\{\-2\}\) and then saturates between4×10−24\\times 10^\{\-2\}and5×10−25\\times 10^\{\-2\}throughL=1000L\{=\}1000, while traceMAE\\mathrm\{MAE\}climbs monotonically \(2\.4×10−32\.4\\times 10^\{\-3\}atL=600L\{=\}600to1\.9×10−21\.9\\times 10^\{\-2\}atL=1000L\{=\}1000\) and gate\-path agreement drifts down from1\.01\.0to0\.9680\.968\. Scalar\-grid\-exactness nevertheless holds near90%90\\%across the entire range from500500to10001000\. The model does not smear all values uniformly but instead loses a minority \(∼10%\{\\sim\}10\\%\) of scalars that drift increasingly far from grid\. The separation between the exact short\-horizon regime and the diverged long\-horizon regime is statistically unambiguous \(finalMAE\\mathrm\{MAE\}0atL≤320L\\leq 320versus4\.2×10−24\.2\\times 10^\{\-2\}atL≥600L\\geq 600, Mann–WhitneyUUtest,p≈5×10−57p\{\\approx\}5\\times 10^\{\-57\},n=160n\{=\}160versus120120pooled benchmark samples\)\. Thus the wider\-state profile exhibits*progressive, bounded degradation*past its training horizon\. This is a soft extrapolation limit rather than a hard collapse, which reinforces the use of the length\-robust 16\-wideQAT8profile as the primary low\-precision benchmark\. A controlled training ablation \(below\) shows that this limit is set by the training horizon of this particular trained instance \(programs of at most 40 steps\) rather than by the wider state itself, and is removed by training at a modestly longer horizon\.

Placing every family on a matched evaluation horizon fromL=20L\{=\}20toL=1000L\{=\}1000makes the comparison symmetric \(Supplementary Fig\.[S2](https://arxiv.org/html/2607.10021#Sx1.F2)\)\. The breakdown is not a function of*evaluation*length per se \(every profile is exact through∼500\{\\sim\}500steps\), but appears only for the short\-horizon\-trained 32\-wide instance at long evaluation lengths, while the controlled ablation below shows that the governing factor is the*training*horizon rather than state width\. AtW=16W\{=\}16the non\-QAT8baseline is bit\-exact at every length \(final and traceMAE\\mathrm\{MAE\}0,100%100\\%scalar\-grid\-exact,100%100\\%tolerance\), and theQAT8families hold finalMAE\\mathrm\{MAE\}in the10−310^\{\-3\}band with effectively exact operation paths throughL=1000L\{=\}1000\. Doubling the continuous state toW=32W\{=\}32keeps execution exact only throughL=400L\{=\}400and then introduces the endpoint error, scalar\-grid loss and gate drift documented above\. A qualification is that even theW=16W\{=\}16non\-QAT8instance shows a small operation\-path dip atL≥900L\\geq 900\(to∼96%\{\\sim\}96\\%\) while its outputs remain bit\-exact, consistent with occasional routing through an output\-equivalent opcode at extreme lengths rather than an execution error\. The short\-horizon 32\-wide onset coincides with a fixed*absolute*step \(≈494\{\\approx\}494, Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)c\) rather than a fixed fraction of the program, which is the signature of a learned\-horizon boundary rather than a width\-capacity bound\. This reading is confirmed directly by the controlled training ablation that follows\.

To investigate why the 32\-wide trained instance deviates at long horizons and whether the wider state is fundamentally limited, we retrained the identical 32\-wide architecture \(non\-QAT8, fixed seed\) while changing one factor at a time and benchmarked each variant across the same sweep fromL=20L\{=\}20toL=1000L\{=\}1000\(Supplementary Fig\.[S16](https://arxiv.org/html/2607.10021#Sx1.F16)and Table[S1](https://arxiv.org/html/2607.10021#Sx1.T1)\)\. Every variant is bit\-exact through at leastL=520L\{=\}520, but the long\-horizon behaviour separates cleanly by*training horizon*\. Training on programs up to 80 or 160 instructions removes the deviation entirely\. Both are bit\-exact \(final and traceMAE\\mathrm\{MAE\}exactly0\) throughL=1000L\{=\}1000\. By contrast, neither memory capacity nor training duration accounts for it\. Varying the memory slots while keeping the maximum training length at 40 instructions is non\-monotonic and follows no capacity law \(halving to128128slots remains bit\-exact throughL=1000L\{=\}1000, while doubling to512512gives only a mild late drift, finalMAE\\mathrm\{MAE\}9\.2×10−49\.2\\times 10^\{\-4\}atL=1000L\{=\}1000\), and*tripling*the training epochs to4545at the same maximum training length does not remove the deviation and in fact*worsens*the far\-horizon error \(7\.0×10−27\.0\\times 10^\{\-2\}atL=1000L\{=\}1000, the largest of any variant\), consistent with overfitting to the short trained length\. The variability among the variants trained up to 40 instructions \(some bit\-exact, some developing long\-horizon drift\) is itself consistent with a marginal, seed\-sensitive learned\-horizon boundary at the short horizon that a longer training horizon removes decisively\. We therefore conclude that the wider\-state long\-horizon breakdown is a*learned training\-horizon limit*of the short\-horizon trained instance, not a capacity bound of theW=32W\{=\}32state\. The3232\-wide executor is not fundamentally length\-limited, and a modestly longer training horizon makes it bit\-exact across the full sweep, matching the1616\-wide profile\. The≈494\{\\approx\}494\-step onset reported above is therefore specific to the instance trained with maximum length 40 rather than a fixed architectural constant\.

### 3\.5The control path is preserved while error localizes in the datapath

The supplementary execution diagnostics explain why the aggregate curves in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)separate only under particular conditions\. Across soft and hard decoding, gate confidence, per\-operation calibration and per\-step trace divergence \(Supplementary Figs\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)to[S6](https://arxiv.org/html/2607.10021#Sx1.F6)\), the same mechanism appears\. The discrete*control*path \(which operation is executed at each step\) is preserved across decoding modes, lengths and width profiles, whereas residual error localizes in the continuous*datapath*\. The 32\-wide extrapolation series combines a two\-seed low\-length grid \(L≤320L\\leq 320\) with a three\-seed long\-horizon sweep \(L≥400L\\geq 400\), without additional training\.

A neural executor can be evaluated with stochastic \(soft\) or deterministic \(hard\) gates, and the critical question is whether the two modes disagree on*what*is executed\. Supplementary Fig\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)b shows that soft\-vs\-hard gate\-sequence agreement stays at≥99\.9%\\geq 99\.9\\%across the range fromL=20L\{=\}20toL=1000L\{=\}1000for all five profiles, so both modes traverse the same opcode sequence\. The final states nevertheless drift apart \(Supplementary Fig\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)a\)\. The soft\-vs\-hard finalMAE\\mathrm\{MAE\}sits at the10−410^\{\-4\}level for the 16\-wide non\-QAT8andQAT8instances throughL≈600L\{\\approx\}600and grows to4\.2×10−44\.2\\times 10^\{\-4\}and2\.8×10−32\.8\\times 10^\{\-3\}respectively byL=1000L\{=\}1000, while the 32\-wide extrapolation instance jumps from1\.7×10−41\.7\\times 10^\{\-4\}atL=400L\{=\}400to5\.5×10−25\.5\\times 10^\{\-2\}atL=700L\{=\}700\. The long\-program ValueMemoryQAT8instance is the limiting case\. Its soft and hard executions are numerically identical at essentially every length \(soft\-vs\-hard finalMAE\\mathrm\{MAE\}∼10−16\{\\sim\}10^\{\-16\}, at the floating\-point floor, e\.g\. atL=1000L\{=\}1000\), with a minority of individual benchmark batches \(e\.g\. near the range fromL=80L\{=\}80toL=260L\{=\}260\) showing a small non\-floor residual up to∼2×10−5\{\\sim\}2\\times 10^\{\-5\}\. The two panels together establish that the soft and hard discrepancy is a continuous\-datapath effect, never a difference in opcode selection\.

Additionally, Supplementary Fig\.[S4](https://arxiv.org/html/2607.10021#Sx1.F4)shows why the datapath drift appears only at long horizons\. Gate entropy \(Supplementary Fig\.[S4](https://arxiv.org/html/2607.10021#Sx1.F4)a\) and the top\-two gate margin \(Supplementary Fig\.[S4](https://arxiv.org/html/2607.10021#Sx1.F4)b\) are flat, with near\-zero entropy and unit margin, throughL≈400L\{\\approx\}400for all profiles, after which probability mass begins to spread\. Counter\-intuitively, the bit\-exact non\-QAT8run is the*least*soft\-confident at extreme lengths \(entropy0\.0400\.040, margin0\.9640\.964atL=1000L\{=\}1000\), theQAT8family is intermediate \(entropy0\.0140\.014, margin0\.9880\.988\), and the long\-program ValueMemory run is essentially unaffected \(entropy∼2×10−6\{\\sim\}2\\times 10^\{\-6\}, margin1\.0001\.000at every length\)\. Read against Supplementary Fig\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)b, this isolates the soft\-mode calibration loss of[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)c as a spreading of gate*probabilities*, not a change in the*argmax*\. The most numerically exact model spreads the most probability mass while still selecting the correct opcode at essentially every step\.

The Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)localizes the error to particular opcodes\. Summarized across the eight operations, operation accuracy \(under soft\-gate decoding\) holds at100%100\\%throughL≈500L\{\\approx\}500for the 16\-wide profiles and declines only mildly thereafter \(Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)a\), while per\-operation calibration falls from−log10⁡ECE≈7\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 7to≈4\{\\approx\}4for every family except the long\-program ValueMemory track, which holds≈8\{\\approx\}8throughout \(Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)b\)\. The per\-opcode heatmaps make the structure explicit\. For the 16\-wideQAT8family onlyADDloses accuracy \(95\.7%95\.7\\%atL=1000L\{=\}1000, while the other seven opcodes remain100%100\\%\), andADDis also the worst\-calibrated row \(Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)c,d\)\. For the 32\-wide extrapolation profile the loss concentrates inMUL\(64\.0%64\.0\\%\) andSHR\(66\.5%66\.5\\%\) atL=1000L\{=\}1000, withADDmildly affected \(97\.4%97\.4\\%\) and the remaining five opcodes exact \(Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)e,f\)\. The carry\- and shift\-heavy arithmetic is therefore the first to leave the fixed\-point grid\. The degradation is operation\-specific rather than a uniform collapse\. Crucially, calibration degrades*ahead of*accuracy, and reading the two heatmap rows against each other exposes this ordering\. AtL=1000L\{=\}1000most opcodes still classify exactly yet shed up to∼3\{\\sim\}3orders of magnitude of calibration score\. In the 16\-wideQAT8family every opcode exceptADDholds100%100\\%accuracy whileANDandSHLfall to values from−log10⁡ECE≈2\.6\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 2\.6to−log10⁡ECE≈2\.7\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 2\.7\(from values between≈4\{\\approx\}4and≈6\{\\approx\}6atL=100L\{=\}100, Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)c,d\), and in the 32\-wide extrapolation profileORremains100%100\\%accurate but drops to−log10⁡ECE≈2\.3\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 2\.3whileSHL,SUBandXORstay both exact and well\-calibrated \(−log10⁡ECE≳4\.6\-\\log\_\{10\}\\mathrm\{ECE\}\\gtrsim 4\.6, Supplementary Fig\.[S5](https://arxiv.org/html/2607.10021#Sx1.F5)e,f\)\. Only the carry/shift\-heavyADD,MULandSHR\(where the probability spread grows large enough to flip the hard argmax\) lose accuracy as well\. This ordering follows directly from the two metrics measuring different quantities\. Operation accuracy depends only on whether the correct opcode remains the argmax, whereasECE\\mathrm\{ECE\}penalises the full confidence\-versus\-correctness gap, so the long\-horizon spreading of gate probability documented in Supplementary Fig\.[S4](https://arxiv.org/html/2607.10021#Sx1.F4)\(rising entropy, shrinking top\-two margin\) erodes calibration first and changes the decision only in the extreme\. Per\-operation calibration is therefore the sensitive, leading indicator of approaching the execution horizon, and operation accuracy the lagging, coarser one\. This is consistent with the same probability\-spread\-not\-argmax\-flip mechanism seen in the soft\-vs\-hard gate agreement of Supplementary Fig\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)b\.

Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)resolves*where within a program*the error appears\. For the 16\-wideQAT8families the per\-step traceMAE\\mathrm\{MAE\}rises within the first∼10%\{\\sim\}10\\%of execution to the range from2×10−32\\times 10^\{\-3\}to3×10−33\\times 10^\{\-3\}and then stays flat for the remainder, while the non\-QAT8instance remains at the10−710^\{\-7\}floor \(bit\-exact at every step\) \(Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)a\)\. TheQAT8heatmap confirms that this early plateau is essentially length\-independent \(Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)b\)\. The 32\-wide extrapolation profile behaves qualitatively differently\. Its trace error is at the floor for the first half of long programs and then rises sharply \(Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)a,c\)\. Across the matched low\-length grid \(L≤320L\\leq 320\) it stays pinned at the trace\-MAE\\mathrm\{MAE\}floor at every step \(the uniformly dark band at the bottom of Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)c\), confirming that the wider\-state breakdown is a horizon effect\. It appears only past the trained step budget rather than being a generic width penalty that is merely diluted at short lengths\. The heatmap boundary is*diagonal*\(Supplementary Fig\.[S6](https://arxiv.org/html/2607.10021#Sx1.F6)c\) because the onset is at a fixed absolute step\. AcrossL∈\{500,…,1000\}L\\in\\\{500,\\dots,1000\\\}the first step exceeding a10−310^\{\-3\}trace error is step≈494\{\\approx\}494in every case, which maps to normalized progress0\.990\.99atL=500L\{=\}500but0\.490\.49atL=1000L\{=\}1000\. The wider\-state breakdown is thus a training\-horizon limit \(∼500\{\\sim\}500executed steps for this instance trained on programs of at most 40 steps, and removed by longer\-horizon training, Supplementary Table[S1](https://arxiv.org/html/2607.10021#Sx1.T1)\), whereas the 16\-wide target shows soft, bounded, non\-accumulating error within the same horizon\.

### 3\.6Robustness tests, cost\-aware execution and architectural limits

The length benchmark and matched replay analysis establish the main positive result\. With visible opcodes and an appropriate low\-precision reference, the executor preserves the symbolic operation path over long programs\. We next change one condition at a time to identify which part of the implemented system carries each result\.[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)therefore brings together four contrasts involving corrupted inputs, equivalent lower\-cost programs, architecture ablations and hidden\-opcode memory tasks\. The hidden\-opcode memory\-pressure condition is the negative control for general program induction\. When the operation cue is withheld, the model must infer latent operation and memory\-use structure rather than execute an observed instruction stream\. Several control measurements are saturated and are more informative as text than as separate panels\. Matched fixed\-point replay is exact on all hard device\-reference splits, min\-energy and any\-valid operation paths are fully gate\-aligned in the energy\-choice evaluation, and most structured comparison architectures solve the baseline visible\-opcode distribution\. These saturated controls anchor the interpretation of the non\-saturated cases, where a cue is removed, the reference semantics change or the task becomes memory\-mediated\.

Input perturbations affect the continuous datapath rather than the opcode cue\. The robustness tests add bit flips or least\-significant\-bit \(LSB\)\-scaled perturbations to the model inputs during evaluation, where LSB denotes the simulated input quantization scale rather than a physical circuit bit\. They do not simulate radiation, thermal noise, circuit faults or measured device noise\. The opcode field and the supervised operation gate remain present, so these perturbations primarily disturb the continuous register values that feed the fixed operation bank and destination writeback\. Accordingly, the strongest reported perturbations raise final error to the range from7×10−37\\times 10^\{\-3\}to8×10−38\\times 10^\{\-3\}and reduce tolerance faithfulness to the range from40%40\\%to60%60\\%, while the symbolic operation path remains essentially intact \([fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)a and Supplementary Fig\.[S8](https://arxiv.org/html/2607.10021#Sx1.F8)\)\. The mechanism is therefore not a sudden collapse of the controller\. It is value drift in the differentiable register datapath under corrupted inputs, with the categorical operation selector still anchored by the visible instruction stream\.

Equivalent\-program tasks change the correct reference path\. The energy\-choice benchmark is not a test of canonical\-trace imitation\. Each sample stores a canonical program and a finite set of admissible lower\-cost alternatives generated by the symbolic data generator\. Under the min\-energy policy, the correct behaviour is to leave the canonical path whenever a lower\-proxy\-cost trace reaches the same final state\. Consequently, canonical\-path agreement can be low or zero without indicating an error\. The model is being scored against a different, valid symbolic execution\. In the energy\-choice evaluation, min\-energyQAT8execution has finalMAE\\mathrm\{MAE\}5\.84×10−45\.84\\times 10^\{\-4\}, any\-valid traceMAE\\mathrm\{MAE\}4\.57×10−44\.57\\times 10^\{\-4\}, zero mean energy gap relative to the minimum\-energy reference and a 38\.6% mean proxy\-energy reduction relative to canonical execution \(Table[5](https://arxiv.org/html/2607.10021#S3.T5)\)\.[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)b therefore plots proxy\-energy saving against any\-valid trace error, while the saturated min\-energy and any\-valid gate agreement is stated in the caption rather than used as a separate heatmap\.

Architecture ablations identify what the trace supervision contributes\. The architecture comparison benchmark comparesGRU\-NTM, no\-gate\-loss, no\-memory, transformer\-NTM, transformer\-scratchpad, temporal convolution, graph, temporal graph and state\-space variants on the same visible\-opcode task family \(Table[6](https://arxiv.org/html/2607.10021#S3.T6)and Supplementary Fig\.[S12](https://arxiv.org/html/2607.10021#Sx1.F12)\)\. These comparisons are architectural diagnostics rather than capacity\-matched pairwise comparisons\. Parameter counts and memory interfaces differ across variants, so the supported inference is mechanistic rather than a claim of capacity\-controlled superiority\. Because several structured controllers reach the numerical display floor on this baseline task distribution, the informative evidence is not another near\-floor error measurement\. It is the contrast introduced by the diagnostic controls\. Removing the gate loss leaves the state and trace losses to shape the router indirectly\. The network can reduce register error while allowing the named operation logits to drift away from the reference operation sequence\. This produces finalMAE\\mathrm\{MAE\}0\.0412, traceMAE\\mathrm\{MAE\}0\.0489 and gate agreement 0\.745 atL=200L=200\. The transformer scratchpad baseline is limited by a different implemented interface\. It predicts traces without exposing theALUgate and writeback pathway, so even when it learns part of the state trajectory it cannot provide the auditable operation path required by the symbolic executor\. Thus the ablation result is not merely that one model has higher MAE\. It shows that gate supervision and an explicit symbolic interface are the mechanisms that make the computation inspectable\.

Hidden\-opcode memory pressure removes the cue that visible\-opcode execution relies on\. The memory\-pressure benchmark masks opcode hints and evaluates delayed copy, associative lookup, pointer chasing, stack\-style reversal and long hidden\-memory reversal\. This changes the problem from executing a visible program to inferring a latent operation and memory\-use pattern from register transitions and delayed state dependencies\. On held\-out memory\-pressure tasks and lengths, the mainGRU\-NTMmodel reaches finalMAE\\mathrm\{MAE\}0\.343 and the no\-memory ablation reaches 0\.364\. ValueMemory improves the held\-out task and length split to 0\.301, andQAT8ValueMemory further improves it to 0\.243, but this remains far from the visible\-opcode regime\. The detailed task split explains why \([fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)c,d and Supplementary Figs\.[S13](https://arxiv.org/html/2607.10021#Sx1.F13),[S14](https://arxiv.org/html/2607.10021#Sx1.F14)\)\. Stack push and pop cases benefit from an addressable value store because they require repeated local retrieval and update, whereas long hidden\-memory reversal requires sustained temporal binding, ordered delayed writes and operation inference over a much longer latent sequence\. The low gate agreement in these panels is therefore not a contradiction of the near\-exact visible\-opcode gate result\. It is the direct measurement of the harder condition in which the operation cue is withheld\.

### 3\.7The cross\-benchmark signature mechanisms

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure3_stress_cost_limits.png)Figure 3:Robustness tests, cost\-aware execution and hidden\-memory limits\.Metric formulas are defined in[section˜2\.3](https://arxiv.org/html/2607.10021#S2.SS3), and the energy\-choice, architecture\-comparison and memory\-pressure protocols are defined in[section˜2\.8\.14](https://arxiv.org/html/2607.10021#S2.SS8.SSS14)\.\(a\)Simulated model\-input perturbations test whether bit\-flip and LSB\-noise corruptions mainly affect continuous register values or the symbolic execution path\.\(b\)Equivalent\-program cost choice tests whether the executor can select a lower\-proxy\-cost valid trace rather than merely imitate the canonical trace\.\(c\)Hidden\-opcode memory\-pressure splits test how the main model, ValueMemory,QAT8ValueMemory and no\-memory ablation behave when opcode cues are withheld\.\(d\)Held\-out memory\-task boundaries identify which delayed\-memory tasks benefit from ValueMemory and which remain difficult under hidden\-opcode conditions\.\(e\)The cross\-benchmark signature summarizes the dominant mechanism in each stress condition by comparing state error, trace error, gate\-path loss, tolerance loss and cost saving\. Detailed visual\-scaling conventions and saturated\-metric interpretations are given in the surrounding text and Supplementary note 6\.[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)e provides a mechanism map\. State and trace entries use the measuredMAE\\mathrm\{MAE\}values\. Gate\-path loss is11minus gate agreement\. Tolerance loss is11minus tolerance faithfulness\. Cost saving is shown as a benefit\. Grey dashes indicate quantities outside a protocol, such as tolerance scoring for the energy\-choice row, and the scratchpad row is marked as having no explicit operation path because the baseline does not expose the namedALUgate trace\. Read from left to right, the row mechanisms are distinct\. CoreQAT8execution retains the symbolic path but shows continuous\-reference drift under low precision\. Input perturbations affect values while preserving the opcode cue\. Energy\-choice succeeds under valid\-path semantics and adds cost reduction\. NoGateLoss removes the categorical constraint that pins operation identity\. Scratchpad prediction lacks an inspectable gate and writeback interface\. Hidden\-opcode memory pressure combines state, trace, gate and tolerance degradation because it asks the model to infer latent operations and delayed memory use rather than execute a visible instruction stream\.

[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)summarizes the robustness, cost\-aware execution and hidden\-memory\-limit analyses\. Metric formulas are defined in[section˜2\.3](https://arxiv.org/html/2607.10021#S2.SS3)\. The energy\-choice, architecture\-comparison and memory\-pressure protocols are defined in[section˜2\.8\.14](https://arxiv.org/html/2607.10021#S2.SS8.SSS14)\. Saturated and contrasting metrics are interpreted in Supplementary note 6\.

[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)a reports robustness under simulated model\-input perturbations\. The upper curve reports finalMAE\\mathrm\{MAE\}, and the lower curve reports tolerance faithfulness for clean execution, bit\-flip perturbation and LSB\-noise perturbation at two program lengths\. Error bars are benchmark\-batch standard deviations\.

[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)b reports the equivalent\-program cost\-choice benchmark\. The left subpanel shows proxy\-energy reduction relative to canonical execution for each task family\. The right subpanel compares canonical\-trace error and any\-valid\-trace error on the same rows\. Min\-energy gate agreement and any\-valid gate agreement are 100% in this run\. Canonical\-path agreement is low or zero when the selected lower\-cost path differs from the canonical trace\.

[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)c reports hidden\-opcode memory\-pressure splits\. Curves show finalMAE\\mathrm\{MAE\}for the main model, ValueMemory,QAT8ValueMemory and no\-memory ablation across seen, length\-held\-out and task\-held\-out splits\.

[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)d reports the held\-out memory\-task boundary\. The upper subpanel reports finalMAE\\mathrm\{MAE\}, and the lower subpanel reports gate agreement for long hidden\-memory reversal and stack push and pop under seen and held\-out lengths\. ValueMemory improves stack\-style held\-out cases, but long hidden\-memory reversal remains difficult\.

[Figure˜3](https://arxiv.org/html/2607.10021#S3.F3)e reports the cross\-benchmark signature\. Rows summarize the principal 16\-wideQAT8family atL=1000L\{=\}1000, the worst simulated input\-perturbation condition, the energy\-choice benchmark under any\-valid scoring, the two informative architecture negative controls, NoGateLoss and scratchpad, and the strongestQAT8ValueMemory model on the hardest memory\-pressure split\. Dot size and colour encode the magnitude of state error, trace error, gate\-path loss and tolerance loss\. Green dots encode cost saving as a positive benefit\. For visual scaling, state and traceMAE\\mathrm\{MAE\}are log\-normalized between10−310^\{\-3\}and3×10−13\\times 10^\{\-1\}\. Gate\-path loss is11minus gate agreement\. Tolerance loss is11minus tolerance faithfulness\. Additionally, the cost saving is the fractional proxy\-energy reduction, grey dashes indicate metrics that are outside that benchmark protocol rather than missing evaluations\. “none” marks the scratchpad baseline’s absence of an explicit operation path, and the right\-hand annotation states the dominant interpretation of each row\.

Table 5:Energy\-choice execution summary\.Energy is a dimensionless simulation proxy, not measured device energy\.TaskFinalMAEAny\-validtrace MAECanonicalenergyModelenergySavingall0\.0005840\.0004571412\.99868\.2738\.6%micro\-op fusion0\.0001750\.0002971504\.87698\.5053\.6%redundant noop0\.0008180\.0006181324\.64682\.7148\.5%skip identity ops0\.0000000\.0000001489\.140\.00100\.0%memory copy min\-energy0\.0008700\.0007721410\.571341\.764\.9%Table 6:Representative architecture metrics atL=200L=200\.ModelParametersFinalMAETraceMAEGateagreementGRU\-NTMmain1608600\.00000\.00001\.000GRU\-NTMQAT81608600\.00380\.00451\.000No gate loss1608600\.04120\.04890\.745No memory1608600\.00000\.00001\.000Transformer\-NTM4825240\.00000\.00001\.000Transformer scratchpad4387840\.05870\.0910no explicit gatesTCN\-NTM2841240\.00000\.00001\.000Graph\-DCPU1471640\.00000\.00001\.000TemporalGraph\-DCPU2462360\.00000\.00001\.000SSM\-DCPU1117080\.00000\.00001\.000
### 3\.8Symbolic rollout diagnostics for the selected stack

Aggregate figures \([figs\.˜2](https://arxiv.org/html/2607.10021#S3.F2),[3](https://arxiv.org/html/2607.10021#S3.F3)and[6](https://arxiv.org/html/2607.10021#S3.F6)and Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)\) establish the benchmark\-level outcome of the non\-spiking executor, the memory\-pressure variant and the closed\-loop controller\. A separate question is whether those outcomes correspond to interpretable executions on individual programs\.[Figure˜4](https://arxiv.org/html/2607.10021#S3.F4)therefore reports machine\-visible observables including operation\-gate alignment, router entropy, operation probabilities, memory addressing weights and per\-step register trace error without relying on hidden\-unit activations\.

For clarity, we briefly define the plotted variables\. At each program steptt, the reference opcode isotrefo\_\{t\}^\{\\mathrm\{ref\}\}and the model produces gate logitsℓt\\ell\_\{t\}and soft gate probabilitiespt=softmax​\(ℓt/τ\)p\_\{t\}=\\mathrm\{softmax\}\(\\ell\_\{t\}/\\tau\)\. Operation\-gate match ismt=𝟏​\[arg⁡maxo⁡ℓt,o=otref\]m\_\{t\}=\\mathbf\{1\}\[\\arg\\max\_\{o\}\\ell\_\{t,o\}=o\_\{t\}^\{\\mathrm\{ref\}\}\]\. Router entropy isHt=−∑opt,o​log⁡\(max⁡\(pt,o,10−12\)\)H\_\{t\}=\-\\sum\_\{o\}p\_\{t,o\}\\log\(\\max\(p\_\{t,o\},10^\{\-12\}\)\), displayed aslog10⁡\(Ht\+ε\)\\log\_\{10\}\(H\_\{t\}\+\\varepsilon\)\. Operation heatmaps plotlog10⁡P​\(op\)\\log\_\{10\}P\(\\mathrm\{op\}\)from the same soft probabilities with a10−410^\{\-4\}floor\. Memory\-addressing heatmaps plot deviation from uniform,Δ​w=w−1/K\\Delta w=w\-1/K, forKKmemory slots\. Per\-step trace error isMAEt=meanr,w​\|rt,r,wpred−rt,r,wref\|\\mathrm\{MAE\}\_\{t\}=\\mathrm\{mean\}\_\{r,w\}\\lvert r^\{\\mathrm\{pred\}\}\_\{t,r,w\}\-r^\{\\mathrm\{ref\}\}\_\{t,r,w\}\\rvertover registersrrand scalar componentsww\. In columnC, the joint plot shows episode return versus final MAEMAEfinal\\mathrm\{MAE\}^\{\\mathrm\{final\}\}, and success is𝟏​\[MAEfinal≤10−2\]\\mathbf\{1\}\[\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\\leq 10^\{\-2\}\]\.

ColumnAis an open\-loop, reference\-conditioned rollout of the principalGRU\-NTMQAT8executor on a*reverse*program \(L=60L=60, seed 7, selected from three candidate seeds by highest gate agreement and lowest mean trace MAE\)\. Every reference step uses XOR, so the opcode strip is collapsed to an in\-panel label\. The gate/router row reports two complementary views of symbolic alignment, namely hard\-gate agreement summarized as a badge and soft routing uncertainty vialog10⁡\(Ht\+ε\)\\log\_\{10\}\(H\_\{t\}\+\\varepsilon\)for router entropyHt=−∑opt,o​log⁡pt,oH\_\{t\}=\-\\sum\_\{o\}p\_\{t,o\}\\log p\_\{t,o\}with a subtle area fill for readability\. On this exemplar, operation\-gate match is exact \(mt≡1m\_\{t\}\\equiv 1, gate agreement=1\.0=1\.0\) while entropy begins near a numerical floor and then rises episodically late in the program, indicating that the temperature\-scaled softmax distribution can temporarily broaden even when the hard decision remains reference\-aligned\. BecauseP​\(op\)P\(\\mathrm\{op\}\)is degenerate for constant XOR, the operation panel instead shows reference register\-operand routing \(srca, srcb, dst\) over time, making explicit that the executor is still performing structured register selection even without opcode variation\. NTM read/write weights are indistinguishable from uniform on this trace, showing that this example is solved through register routing and local writeback rather than selective slot addressing\. Because the operation probabilities and NTM addressing are uniform on this trace, the displayed diagnostic is a per\-register trace\-MAE\\mathrm\{MAE\}map\. The bottom trace plot shows that register drift remains modest \(mean trace MAE≈4\.9×10−3\\approx 4\.9\\times 10^\{\-3\}\), with a light rolling\-mean overlay to distinguish local spikes from longer\-term accumulation\.

The*reverse*exemplar is useful because its reference control flow is simple \(constant opcode\) while its data movement is non\-trivial\. The executor must repeatedly route operands and update destinations in the correct order\. A case with uniform NTM addressing makes the explicit interpretability point that*external memory is not always the mechanism*, even in an NTM\-augmented architecture\. When the task can be solved from registers and local instruction structure, the auditable objects are gates, operand routing and register\-level error rather than slot selection\. This prepares the comparison to memory pressure, where addressing becomes selective and therefore scientifically meaningful rather than an always\-on visualization\.

ColumnBapplies the same layout to the strongest memory\-pressure model,QAT8ValueMemory, on a masked\-opcode*pointer\-chase*program \(L=40L=40, seed 21\)\. Opcode one\-hot hints are masked while register operands remain visible, and a slim strip marks reference opcode segments without overprinting\. Unlike columnA, gate agreement is high but not exact \(97\.5%97\.5\\%\), so the gate/router row uses dual axes with operation\-gate matchmtm\_\{t\}on the left andlog10⁡\(Ht\+ε\)\\log\_\{10\}\(H\_\{t\}\+\\varepsilon\)on the right, again with a light entropy fill to emphasize oscillatory structure\. The operation\-probability heatmap \(logP10​\(op\)\{\}\_\{10\}\\,P\(\\mathrm\{op\}\)\) shows that the model maintains a structured distribution over plausible operations despite hidden opcodes, and that uncertainty varies systematically with reference opcode\-transition boundaries\. Crucially, the memory rows become informative because value\-memory read/write weights deviate from uniform in sparse, repeating bands, consistent with pointer\-style retrieval and periodic updates to a small subset of slots plotted asΔ​w=w−1/K\\Delta w=w\-1/K\. The trace\-MAE curve decays rapidly and remains near zero for most steps \(mean≈1\.7×10−3\\approx 1\.7\\times 10^\{\-3\}\), connecting*interpretable memory use*to low register error on this exemplar while remaining consistent with aggregate degradation on harder held\-out memory families \([fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)d\)\.

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/figure_winning_stack.png)Figure 4:Symbolic rollout diagnostics for the selected non\-spiking stack\.Rollout variables, trace extraction and candidate\-control protocol are defined in[sections˜3\.8](https://arxiv.org/html/2607.10021#S3.SS8)and[2\.7](https://arxiv.org/html/2607.10021#S2.SS7)\.\(A\)Open\-loopGRU\-NTMQAT8rollout on*reverse*\(L=60L=60, seed 7\): constant reference opcode XOR \(in\-panel label\);log10\\log\_\{10\}router entropy with a 100% gate\-match badge \(area fill for readability\); operand routing for the two source registers and destination register \(srca, srcb, dst\) in the constant\-XOR program; NTM addressing is uniform so per\-register trace MAE is shown instead; per\-step trace MAE with rolling mean\.\(B\)Open\-loopQAT8ValueMemory rollout on masked\-opcode*pointer\-chase*\(L=40L=40, seed 21\): segmented reference opcode strip; dual\-axis gate match andlog10\\log\_\{10\}router entropy \(with area fill\);log10\\log\_\{10\}operation probabilities;Δ\\Deltavalue\-memory read/write weights, whereΔ\\Deltais deviation from a uniform memory\-slot distribution; per\-step trace MAE with legend\.\(C\)Closed\-loop candidate control overN=1024N=1024episodes \(return versus final MAE\): non\-success density with marginal histograms and success overlay, per\-task success bars, and paired heuristic→\\tocandidate lifts for both factorized multilayer perceptron \(MLP\) and factorizedALIFspiking neural network \(SNN\) policies on reference and learned\-QAT8transition suites\. Exemplar repair traces are described in the main text\. ColumnsA–Bare single\-trace reference\-conditioned execution; columnCis the candidate\-control evaluation suite\.ColumnCmoves from single\-trace diagnostics to population\-level control outcomes\. The joint plot showsN=1024N=1024closed\-loop evaluation episodes from the reference\-transition factorized multilayer\-perceptron \(MLP\) candidate controller\. It presents final MAE versus episode return with non\-success density shown by a hexbin and successful episodes overlaid as points, while marginal histograms summarize densities along both axes and the legend reports the success and non\-success counts\. Two clusters emerge, with successes concentrating atMAEfinal≤10−2\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\\leq 10^\{\-2\}and high return while non\-success episodes spread along a diagonal band at larger MAE and low or negative return\. This indicates that return is largely explained by proximity to the target state rather than by diffuse exploration\. The per\-task bar chart reports success rates for the most frequent tasks in the evaluation log and highlights harder families such as shift\-right and low\-level boolean chains even under candidate masking\. Finally, the paired lift panel compares heuristic\-only control with candidate\-masked fine\-tunes using the control summary table\. On the*reference*suite, the factorized MLP improves from11\.7%11\.7\\%to34\.8%34\.8\\%success \(\+23\.0\+23\.0pp\) while the factorized adaptive leaky integrate\-and\-fire \(ALIF\) spiking neural network \(SNN\) improves from8\.4%8\.4\\%to14\.5%14\.5\\%\(\+6\.1\+6\.1pp\)\. On the*learned\-QAT8*backend, the MLP improves from11\.1%11\.1\\%to31\.0%31\.0\\%\(\+19\.8\+19\.8pp\) while the SNN improves from9\.2%9\.2\\%to11\.9%11\.9\\%\(\+2\.7\+2\.7pp\)\. This column is*not*task\-matched to columnsAandB\. It summarizes controllability under candidate\-constrained search across a multi\-task suite rather than replaying the same reference programs\.

Two representative repair traces illustrate the closed\-loop policy \(beam width 4, depth 2, up to 512 candidates per step\)\. A*successful*episode on theshift\_lefttask \(episode 2, one repair step\) applies a single symbolic action,

> SHL R4, R3 \-\> R6

and reachesMAEfinal=0\\mathrm\{MAE\}^\{\\mathrm\{final\}\}=0\. A*non\-successful*episode on shift to right \(episode 1, four repair steps\) instead proposes a short multi\-instruction sequence,

> MUL R0, R3 \-\> R3 \| MUL R6, R5 \-\> R3 \| MUL R5, R3 \-\> R3 \| MUL R6, R5 \-\> R3

which does not recover the target state \(MAEfinal\>10−2\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\>10^\{\-2\}\)\. These examples illustrate that success is determined by whether the candidate\-constrained search finds a short symbolic correction, not by a single scalar summary alone\.

### 3\.9Hybrid spiking\-controller extension

Spiking controllers test whether the same symbolic execution surface can be paired with event\-driven temporal state\. They are not presented as replacements for the non\-spikingQAT8executor\. The implemented design restricts spikes to the controller dynamics\. Instruction and register information are encoded as deterministic current input, theALIFmodule supplies temporal controller memory, and the downstream operation router, continuousALUbank, destination write and ValueMemory or NTM pathways remain the same inspectable symbolic interface used by the non\-spiking models\. This hybrid construction preserves the named operation path while exposing membrane and spike variables that are relevant to future neuromorphic implementations\. Supplementary Fig\.[S15](https://arxiv.org/html/2607.10021#Sx1.F15)summarizes feasibility, and[fig\.˜5](https://arxiv.org/html/2607.10021#S3.F5)provides rollout\-level spike and membrane diagnostics\.

For one symbolic program step, the implemented controller expands the encoded instruction and memory input intoKKmicro\-steps\. The state variables are currentcc, membrane voltageuu, binary spike statezzand adaptive threshold stateaa\. ForALIFneurons, each micro\-step follows\.

ck\+1\\displaystyle c\_\{k\+1\}=αc​ck\+d\+Wrec​zk,\\displaystyle=\\alpha\_\{c\}c\_\{k\}\+d\+W\_\{\\mathrm\{rec\}\}z\_\{k\},\(147\)uk\+1raw\\displaystyle u\_\{k\+1\}^\{\\mathrm\{raw\}\}=αu​uk\+ck\+1,\\displaystyle=\\alpha\_\{u\}u\_\{k\}\+c\_\{k\+1\},\(148\)zk\+1\\displaystyle z\_\{k\+1\}=surrogate​\_​spike​\(uk\+1raw−\(θ0\+β​ak\)\),\\displaystyle=\\mathrm\{surrogate\\\_spike\}\(u\_\{k\+1\}^\{\\mathrm\{raw\}\}\-\(\\theta\_\{0\}\+\\beta a\_\{k\}\)\),\(149\)uk\+1\\displaystyle u\_\{k\+1\}=uk\+1raw​\(1−zk\+1\),\\displaystyle=u\_\{k\+1\}^\{\\mathrm\{raw\}\}\(1\-z\_\{k\+1\}\),\(150\)ak\+1\\displaystyle a\_\{k\+1\}=γ​ak\+zk\+1,\\displaystyle=\\gamma a\_\{k\}\+z\_\{k\+1\},\(151\)matching the implemented spiking\-controller update\. The forward spike is a hard threshold, while the backward pass uses the implemented fast\-sigmoid surrogate gradient\. The returned controller feature is not a raw event list\. It is the mean spike state over theKKmicro\-steps, concatenated with the final membrane state and projected through the controller readout\. The spiking ValueMemory model then computes read weights from the previous spike state, blends the read value into the register operands, routes through the sameALUoperation bank, clamps the writeback to\[0,1\]\[0,1\], and updates the value memory with a soft write address\.

In the memory\-pressure setting, theALIFValueMemory substep\-4 instance reaches held\-out final MAE 0\.447, trace MAE 0\.419, gate agreement 39\.2% and spike rate 23\.7%\. It therefore does not outperform the non\-spikingQAT8ValueMemory baseline\. It serves instead to make the neuromorphic route concrete and inspectable\. Supplementary Fig\.[S15](https://arxiv.org/html/2607.10021#Sx1.F15)reports an 8\-wide feasibility evaluation, the sensitivity to micro\-step count and spike regularization, and the memory\-pressure extension\.[Figure˜5](https://arxiv.org/html/2607.10021#S3.F5)then shows how operation gates, membrane voltage, averaged spikes and trace error evolve on individual programs\.

### 3\.10Interpretable spiking rollout diagnostics

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/figure_1-4.png)Figure 5:Spiking controller rollout diagnostics and closed\-loop episode outcomes\.Spiking variables, rollout extraction and episode\-level control definitions are given in[sections˜3\.10](https://arxiv.org/html/2607.10021#S3.SS10),[2\.6](https://arxiv.org/html/2607.10021#S2.SS6)and[2\.7](https://arxiv.org/html/2607.10021#S2.SS7)\.\(a\)Open\-loop rollout on a held\-out pointer\-chase memory\-pressure program \(L=40L=40, seed 7, masked opcode hints\)\. Top row: reference opcode labels\. Second row: operation\-gate matchmtm\_\{t\}\(left axis\) andlog10\\log\_\{10\}router entropy \(right axis\)\. Third row: hidden\-unit spike raster \(z¯t,i\\bar\{z\}\_\{t,i\}, units sorted by mean rate\)\. Fourth row: membrane potentialut,iu\_\{t,i\}\(display clipped at 2nd–98th percentiles\)\. Bottom row: per\-step trace MAE with optional reference band\.\(b\)Same layout for long reverse with hidden memory \(L=60L=60, seed 7\)\.\(c\)Three\-dimensional membrane landscape for the panel\(a\)rollout with spike markers above the surface \(mean spike rate21\.4%21\.4\\%\)\.\(d\)Closed\-loop evaluation overN=1024N=1024episodes: final register MAE versus mean policy spike rate for a factorizedALIFcontroller with candidate masking and beam search \(success ifMAEfinal≤10−2\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\\leq 10^\{\-2\}; green, success; grey, non\-success; marginal densities shown\)\. Panels\(a–c\)are single\-trace reference\-conditioned execution; panel\(d\)is the multi\-task control evaluation suite\.The aggregateALIFValueMemory metrics set the boundary for the spiking extension on held\-out memory pressure\. The substep\-4 instance reaches final MAE 0\.447, trace MAE 0\.419 and gate agreement 39\.2%, and therefore does not replace the non\-spikingQAT8ValueMemory baseline\. Those scalar metrics do not show how a trained spiking controller behaves on individual programs\.[Figure˜5](https://arxiv.org/html/2607.10021#S3.F5)links symbolic execution, hidden\-unit event dynamics and closed\-loop population statistics in one layout\. The analysis uses the selectedALIFValueMemory trained instance with four micro\-steps per program step, deterministic hard gates, gate temperatureτ=0\.5\\tau=0\.5and masked opcode hints on memory\-pressure programs\. All register errors are computed in normalized\[0,1\]\[0,1\]space, consistent with the reference and benchmark implementation\.

Panels\(a\)and\(b\)report*open\-loop*, trace\-conditioned rollouts on fixed reference programs\. This is not autonomous program synthesis because at each stepttthe model receives the reference instruction stream, with opcode one\-hot masked when required, and the evolving register state, while the neural executor predicts operation gates, register traces, hidden spikes and membrane voltages\. Panel\(a\)shows a held\-out*pointer\-chase*program of lengthL=40L=40\(seed 7\)\. After an initial transient, operation\-gate matchmt=𝟏​\[arg⁡maxo⁡ℓt,o=otref\]m\_\{t\}=\\mathbf\{1\}\[\\arg\\max\_\{o\}\\ell\_\{t,o\}=o\_\{t\}^\{\\mathrm\{ref\}\}\]remains high, while router entropyHt=−∑opt,o​log⁡pt,oH\_\{t\}=\-\\sum\_\{o\}p\_\{t,o\}\\log p\_\{t,o\}withpt,o=softmax​\(ℓt/τ\)p\_\{t,o\}=\\mathrm\{softmax\}\(\\ell\_\{t\}/\\tau\)collapses toward a peaked distribution, plotted aslog10⁡\(Ht\+ε\)\\log\_\{10\}\(H\_\{t\}\+\\varepsilon\)\. The spike raster displays micro\-step\-averaged eventsz¯t,i\\bar\{z\}\_\{t,i\}with hidden units sorted by decreasing mean firing rate, while the membrane heatmap shows the post\-substep voltageut,iu\_\{t,i\}clipped for display between the 2nd and 98th percentiles\. Trace mean absolute error,

MAEt=1\|ℛ\|​W​∑r,w\|rt,r,wpred−rt,r,wref\|,\\mathrm\{MAE\}\_\{t\}=\\frac\{1\}\{\|\\mathcal\{R\}\|W\}\\sum\_\{r,w\}\\left\|r^\{\\mathrm\{pred\}\}\_\{t,r,w\}\-r^\{\\mathrm\{ref\}\}\_\{t,r,w\}\\right\|,\(152\)stays small but exhibits periodic peaks aligned with opcode\-transition boundaries, shown by vertical guides on the heatmaps\. Panel\(b\)applies the same visualization to a harder held\-out*long reverse with hidden memory*program \(L=60L=60, seed 7\)\. Gate match oscillates, spike structure becomes less regular andMAEt\\mathrm\{MAE\}\_\{t\}drifts upward with late\-episode spikes\. The juxtaposition supports a concrete error\-accumulation interpretation\. On the easier pointer structure, the controller remains symbolically aligned with low register drift, whereas under longer hidden\-opcode memory pressure the dominant error is temporal accumulation rather than an isolated catastrophic step\.

Panel\(c\)is a three\-dimensional membrane landscape for thesamerollout as panel\(a\)\. The surface plotsut,iu\_\{t,i\}over program step and sorted unit index, while markers indicate steps withz¯t,i\>0\.5\\bar\{z\}\_\{t,i\}\>0\.5\. Mean spike activity over the episode is21\.4%21\.4\\%in this example\. This view places spike events and membrane voltages in a single geometry, making structured temporal locking visible without relying on separate rasters\. Its interpretation is tied to panel\(a\)rather than to an independent benchmark score\.

Panel\(d\)summarizes a*different*experimental protocol involving closed\-loop symbolic control onN=1024N=1024evaluation episodes drawn from the multi\-task control suite\. A factorizedALIFpolicy, fine\-tuned with candidate\-masked imitation and reinforcement learning, selects actions under a reference CPU transition model with at most512512heuristic candidates per step and beam search with width 4 and depth 2\. Each point shows episode final register MAE to the target state versus the mean policy spike rate accumulated over the episode, and success is defined byMAEfinal≤10−2\\mathrm\{MAE\}^\{\\mathrm\{final\}\}\\leq 10^\{\-2\}\. Successful episodes cluster near zero final MAE, while non\-success episodes spread to larger MAE at similar spike rates\. Marginal densities separate success and non\-success along both axes\. This panel therefore addresses population\-level controllability and the decoupling of mean spiking from target achievement\. It must not be interpreted as a task\-matched replay of panels\(a\)to\(c\)\.

[Figure˜5](https://arxiv.org/html/2607.10021#S3.F5)makes the spiking extension inspectable at the level of operations, registers and spikes rather than only scalar MAE\. It also separates the two regimes visible in the aggregate results\. On an easy masked\-opcode program,ALIFdynamics are structured and the gate path is stable, while on a hard program, trace error grows with the temporal\-binding burden\. The population panel then connects these rollout diagnostics to the closed\-loop controller pathway, showing that spike rate alone does not explain autonomous\-control success\. In the present system, the dominant lever for control is symbolic action search over a constrained candidate set\.

### 3\.11Closed\-loop candidate control

Having established supplied\-program execution, we next test whether the same transition substrate can be used to choose instructions\. A controller observes a current register state and a target register state and selects the next symbolic instruction\. This turns execution into a short\-horizon repair problem\. Success means reaching the target state within a final\-state tolerance, whereas the earlier figures measure whether a supplied program is executed with the correct trace and gate path\. This setting tests whether trace\-verified execution can support controllable action selection\.

Formally, the controller defines an MDP

ℳ=\(𝒮,𝒜,P,R,γ\),\\mathcal\{M\}=\(\\mathcal\{S\},\\mathcal\{A\},P,R,\\gamma\),\(153\)where the transitionPPis either the reference CPU transition or the learned 8\-bitQAT8Neural CPU transition\. The action space contains symbolic instruction tuples\. Candidate\-constrained control defines a state\-dependent candidate set

𝒞​\(s\)⊂𝒜,\\mathcal\{C\}\(s\)\\subset\\mathcal\{A\},\(154\)constructed by symbolic heuristics and local state and target comparisons\. The policy distribution is masked as follows\.

πθ𝒞​\(a∣s\)=πθ​\(a∣s\)​𝟏​\[a∈𝒞​\(s\)\]∑a′∈𝒞​\(s\)πθ​\(a′∣s\)\.\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\\mid s\)=\\frac\{\\pi\_\{\\theta\}\(a\\mid s\)\\mathbf\{1\}\[a\\in\\mathcal\{C\}\(s\)\]\}\{\\sum\_\{a^\{\\prime\}\\in\\mathcal\{C\}\(s\)\}\\pi\_\{\\theta\}\(a^\{\\prime\}\\mid s\)\}\.\(155\)Evaluation optionally uses beam search\. For a beam elementb=\(s1:t,a1:t−1\)b=\(s\_\{1:t\},a\_\{1:t\-1\}\), a candidate action receives score

J​\(b,a\)=log⁡πθ𝒞​\(a∣st\)−10​MAE​\(F​\(st,a\),s⋆\)−wE​E​\(a\)\+𝟏​\[MAE​\(F​\(st,a\),s⋆\)≤ϵ\],J\(b,a\)=\\log\\pi\_\{\\theta\}^\{\\mathcal\{C\}\}\(a\\mid s\_\{t\}\)\-10\\,\\mathrm\{MAE\}\(F\(s\_\{t\},a\),s^\{\\star\}\)\-w\_\{E\}E\(a\)\+\\mathbf\{1\}\[\\mathrm\{MAE\}\(F\(s\_\{t\},a\),s^\{\\star\}\)\\leq\\epsilon\],\(156\)wheres⋆s^\{\\star\}is the target,wEw\_\{E\}is the environment energy weight andϵ\\epsilonis the success tolerance\. The coefficient 10 and the unit success bonus rank immediate target\-error reduction above log\-probability and proxy energy during beam evaluation\. The candidate generator also uses fixed offsets for primitive actions and operation\-tie priors\. These constants are reported as algorithmic search choices rather than as physically derived quantities\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)summarizes three evaluation modes, including direct policy evaluation, beam\-style action selection without candidate fine\-tuning, and candidate\-constrained fine\-tuning followed by candidate\-constrained evaluation\. In the figure labels, “direct” denotes the non\-candidate policy baseline and “cand\.” denotes the candidate\-constrained policy\. On the reference transition, candidate constraints increase factorized MLP success from 11\.7% to 34\.8%\. Beam evaluation alone reaches 18\.8%\. The factorizedALIFSNN improves from 8\.4% to 14\.5% under the same candidate protocol\. On the learnedQAT8transition, the MLP improves from 11\.1% to 31\.0%, while the SNN improves from 9\.2% to 11\.9%\. The paired view reports the same effects as absolute gains\. The gains are \+23\.0 percentage points for the reference MLP, \+19\.8 percentage points for the learned\-QAT8MLP, \+6\.1 percentage points for the reference SNN and \+2\.7 percentage points for the learned\-QAT8SNN\.

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure11.png)Figure 6:Candidate\-constrained symbolic control\.\(a\)Reference\-transition control measures target\-reaching success for MLP andALIFSNN policies under direct, beam and candidate\-constrained evaluation\.\(b\)Learned\-QAT8transition control repeats the same closed\-loop protocol through the learned 8\-bit transition model and relates success to final\-state error\.\(c\)Paired action\-search gain shows the success\-rate improvement from direct evaluation to candidate\-constrained evaluation for each controller/back\-end pair\.\(d\)Residual oracle gap compares achieved success with the remaining gap to an oracle selector under the same task distribution\.\(e\)The per\-task success matrix identifies which symbolic control tasks are solved by each reference and learned\-QAT8MLP/SNN candidate policy\.\(f\)The success\-error\-spike relation compares success rate, final\-stateMAE\\mathrm\{MAE\}and recorded spike rate across controller/back\-end settings\.These results define a control extension rather than a replacement for the open\-loop execution benchmark\. The per\-task matrix separates simple state\-setting and copy\-like tasks from more compositional control families, and the residual oracle\-gap panel quantifies the remaining distance to an oracle action selector under the same task suite, including the harder controller settings from the action\-search analysis\. The remaining gap has two concrete sources in the implemented protocol\. First, an executable action is a tuple of operation, source registers and destination register\. Even after candidate masking, many candidates are locally plausible but do not form the ordered multi\-step repair needed by tasks such as reverse\-pair, copy\-chain or accumulated arithmetic\. Beam scoring uses local, short\-horizon rewards, so it can prefer an immediate reduction in final\-state MAE that blocks a later correction\. Second, in the learned\-QAT8setting, the controller scores actions through an approximate transition model\. Small transition errors can change the ranking of candidate actions even when the underlying open\-loop executor remains trace\-faithful under replay\. The success, error and spike panel shows that mean spike activity alone does not explain controllability\. Policies can have comparable recorded spike activity while producing different final errors and success rates\. The main conclusion is structural\. When the symbolic action space grows, unconstrained neural policies allocate probability mass over many irrelevant instructions\. Candidate generation reintroduces a symbolic prior at decision time and lets neural scoring operate over an inspectable action set\. This supports the central thesis that the strongest systems in this setting are structured hybrids rather than pure black\-box controllers\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)summarizes the candidate\-constrained symbolic\-control extension\. Candidate sets, masked policies, beam scoring, success criteria and oracle\-gap definitions are given in[sections˜3\.11](https://arxiv.org/html/2607.10021#S3.SS11)and[2\.7](https://arxiv.org/html/2607.10021#S2.SS7)\. The figure compares direct policy evaluation, beam\-style action selection and candidate\-constrained fine\-tuning/evaluation for factorized multilayer perceptron \(MLP\) and factorizedALIFspiking neural network \(SNN\) policies\. In the in\-panel labels, “direct” denotes the non\-candidate baseline and “cand\.” denotes candidate\-constrained evaluation\.

In our investigation,[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)a reports reference\-transition control\. Bars show the percentage of episodes reaching the target register state for factorized multilayer perceptron \(MLP\) and factorizedALIFspiking neural network \(SNN\) policies\. The three bars correspond to direct policy evaluation, beam\-style action selection and candidate\-constrained fine\-tuning/evaluation\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)b shows the learned\-QAT8transition control\. The same closed\-loop protocol is run through the learned 8\-bit transition model\. The bars show success and the overlaid line reports the final\-stateMAE\\mathrm\{MAE\}\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)c reports paired action\-search gain\. Each line connects direct policy evaluation to the candidate\-constrained policy for the same controller and transition back\-end pair\. Annotations give absolute success\-rate gains in percentage points\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)d reports the residual oracle gap\. Blue segments show achieved success, and grey segments show the remaining gap to the oracle selector under the same task distribution, including the harder controller settings\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)e reports the per\-task success matrix for reference and learned\-QAT8MLP/SNN candidate policies\. Rows are controller/back\-end families and columns are symbolic control tasks\. Entries are success rates in percent\.

[Figure˜6](https://arxiv.org/html/2607.10021#S3.F6)f reports the success, error and spike relation\. Points compare success rate with final\-stateMAE\\mathrm\{MAE\}across controller/back\-end settings\. Marker size follows the recorded spike\-rate field where available and is used as a visual cue rather than a hardware\-energy measurement\.

Together,[fig\.˜6](https://arxiv.org/html/2607.10021#S3.F6)shows that candidate\-constrained symbolic action search improves short\-horizon repair, with the clearest gains for MLP policies, while the learned transition and spiking controllers define the next control boundary\.

### 3\.12An RV32I base\-integer bridge tests the architecture against a standardized ISA

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure12_rv32i_fixed_multiseed.png)Figure 7:RV32I base\-integer semantic\-control diagnostic\.RV32I decode, deterministic audit/harness, learned\-control heads and architecture\-backed executor definitions are given in the methods section\.\(a\)Program\-level agreement for the symbolic\-predicate controller repeated over seeds 42, 43 and 44\. Step agreement is the joint PC/memory/writeback semantic\-control accuracy over teacher\-trace steps\. Program exact requires every semantic\-control decision in a sequence to be correct\. Error bars show s\.d\. across seeds\.\(b\)Targeted semantic\-control rescue\. Grey bars show the pre\-rescue RV32I learned\-control diagnostic values used to identify the weak modes; green bars show the symbolic\-predicate multi\-seed mean with s\.d\. error bars\. Numeric labels give the pre\-rescue percentage for grey bars and mean±\\pms\.d\. across seeds for green bars\. Because trap, JALR, load, store and memory\-trap mode accuracies are uniformly100\.0±0\.0%100\.0\\pm 0\.0\\%after rescue, they are reported in the Results text rather than repeated as a separate panel\. The panel evaluates a base\-integer semantic\-control bridge and does not constitute officialRISC\-Vcompliance or arbitraryRISC\-Vbinary execution by the main trained executor\.The preceding experiments use a controlled symbolic register\-machine distribution because it exposes the complete execution trajectory, including operation labels, destination masks, register traces, memory signals and low\-precision replay\. As an external\-validity test, we implemented an isolated RV32I\-facing extension\. The question is deliberately narrower than officialRISC\-Varchitectural compliance\. Can the symbolic neural CPU execution ingredients, including structured instruction representation, recurrent control, value\-addressed memory and learnedALUrouting, be connected to an implemented RV32I base\-integer semantic bridge with explicit PC, memory, writeback and trap semantics?

The bridge decodes 32\-bit RV32I instruction words into opcode, register, function and immediate fields, then applies deterministic state transitions over 32 architectural registers, byte\-addressed memory, a program counter and an explicit trap state\. The audited inventory covers the RV32I base\-integer entries LUI, AUIPC, JAL, JALR, conditional branches, loads, stores, immediateALUoperations, register\-registerALUoperations, FENCE, ECALL and EBREAK\. Register x0 is forced to zero after every step\. The transition implements signed immediate extension, branch and jump target updates, JAL/JALR link behaviour, JALR low\-bit clearing, load/store width and sign\-extension behaviour, alignment checks, out\-of\-bounds memory traps and illegal\-instruction traps\. In this implementation, FENCE is treated as a single\-hart semantic no\-op, and ECALL/EBREAK enter explicit trap states\.

The deterministic RV32I base\-integer bridge passed 40/40 implemented inventory checks, 28/28 edge\-case tests, 55,524/55,524 randomized property checks and 7/7 signature\-memory harness tests\. This deterministic audit validates the reference bridge and harness rather than learned execution\. The harness executes raw instruction words, records a signature\-memory region and supports expected signature, trap and register checks, but it is not yet the fullriscv\-arch\-testcompilation, linking and reporting flow\.

The same RV32I teacher traces then diagnose learned semantic control\. The pre\-rescue RV32I learned\-control diagnostic exposed the failure modes that mattered for inclusion, including trap state, JALR, load/store mode selection, held\-out program\-exact sequences and length extrapolation\. The rescue controller exposes decoded RV32I bitfields and symbolic predicates to the learned heads, including instruction\-family/name indicators, immediate lanes, branch comparison predicates, effective addresses, memory alignment and bounds predicates, jump\-target alignment and destination\-register\-zero predicates\. We repeated this symbolic\-predicate controller over seeds 42, 43 and 44\. Across seeds, hard semantic modes were recovered at100\.0±0\.0%100\.0\\pm 0\.0\\%accuracy for trap, JALR, load, store and memory\-trap decisions\. Program\-level step agreement was100\.0±0\.01%100\.0\\pm 0\.01\\%on held\-out programs,100\.0±0\.02%100\.0\\pm 0\.02\\%on branch/memory challenge programs and99\.2±0\.26%99\.2\\pm 0\.26\\%on length extrapolation\. Program\-exact sequence accuracy was92\.2±2\.7%92\.2\\pm 2\.7\\%,89\.9±3\.5%89\.9\\pm 3\.5\\%and69\.2±9\.9%69\.2\\pm 9\.9\\%on the same three splits, respectively\. For reference, the corresponding pre\-rescue values were 30\.4% held\-out exact, 24\.1% stress exact, 1\.8% length exact, 79\.8% length step agreement, 37\.5% trap, 60\.9% JALR, 81\.4% load and 80\.1% store\. Program\-exact sequence scoring is stricter than step\-level agreement because a single wrong PC, memory or writeback decision can invalidate the whole sequence\. The RV32I result is therefore architecture\-aligned semantic\-control evidence, not reliable execution of arbitraryRISC\-Vbinaries\.

Together, the deterministic bridge and learned\-control diagnostic support a precise extension of the main claim\. The symbolic neural CPU architecture is not confined to synthetic opcodes\. Its structured execution interface can be attached to an RV32I base\-integer semantic substrate when binary decode, PC update, memory behaviour and traps are represented explicitly, and when learned control is trained over architecture\-aligned predicates\. The result is an RV32I base\-integer bridge and learned\-control diagnostic, not a claim that the main trained executor runs arbitraryRISC\-Vbinaries end to end\.

## 4Discussion

The results establish a trace\-verifiable form of neural symbolic execution in which a learned controller updates register\-machine state while exposing the operation path, register trajectory and writeback events required for step\-by\-step inspection\. The object of interest is therefore not merely the final register file, but the complete trajectory of register states, operation gates and writeback events\. On visible\-opcode programs, the selectedGRU\-NTMfamily preserves this execution object with near\-exact hard operation paths, while the primary trained runs maintain exact hard gate agreement across the reported horizon\. The matched fixed\-point reference is central to this interpretation\. When the independent replay uses the same low\-precision writeback grid as theQAT8executor, final\-state and trace disagreement vanish on the hard splits\. The residual drift against the continuous interpreter is therefore a mismatch between continuous writeback semantics and 8\-bit writeback semantics, rather than evidence that the learned executor has lost the symbolic path it was trained to follow\.

The model comparisons show why this result is more than sequence prediction\. The operation\-gate loss is the categorical term that ties each router decision to a named operation\. Removing it leaves the state and trace losses active, so the model can still approximate useful register values, but the operation logits become weakly constrained\. Mixtures in the continuous operation bank can then compensate for endpoint error while erasing the inspectable opcode sequence\. The NoGateLoss ablation therefore degrades trace fidelity and gate agreement for a mechanistic reason, not merely because one loss weight changed\. The scratchpad baseline exposes the complementary limitation\. It predicts register trajectories without a named operation gate or destination\-writeback interface, so its output is a trajectory estimate rather than a replayable symbolic execution trace\. Together, these controls separate endpoint approximation from the processor\-like property tested in this article, namely whether a reader can inspect which operation was selected and which state variable was written at every step\.

The robustness, cost\-aware and memory\-pressure experiments reveal which information supports each behaviour\. Input bit flips and LSB\-scaled perturbations corrupt continuous register values but leave the visible operation cue intact\. The resulting degradation is therefore value drift in the datapath\. Tolerance faithfulness declines and finalMAE\\mathrm\{MAE\}rises, while the categorical operation path remains stable\. Equivalent\-program energy\-choice tasks change the reference problem instead\. A lower\-proxy\-cost valid program can differ from the canonical trace, so canonical agreement is not the appropriate success criterion\. The relevant evidence is any\-valid trace error together with proxy\-energy reduction\. Hidden\-opcode memory pressure removes the operation cue itself\. The model must then infer operation identity, address use and delayed writeback structure from state transitions\. ValueMemory improves stack\-like retrieval and update tasks because it gives the controller an addressable value pathway\. Long hidden\-memory reversal remains difficult because latent operation inference, temporal ordering and delayed destination writes must be solved together over long sequences\. This is the clearest unresolved boundary of the current executor\.

The rollout panels translate aggregate metrics into observable execution mechanisms\. In the selected non\-spiking trace, hard gates are exact while soft router entropy broadens late in the program\. Hard\-gate alignment therefore does not require the soft distribution to be fully degenerate\. The same trace shows that NTM slots can remain uniform when a program is solved through visible instructions, operand routing and local writeback\. In that regime, the operative audit variables are the gates, source and destination registers, and register\-error profiles rather than selective memory slots\. The memory\-pressure rollout shows the opposite regime\. With opcode hints masked, ValueMemory read and write weights become sparse and structured, while operation probabilities vary with the reference opcode segments\. The scalar aggregate is therefore linked to an interpretable mechanism rather than remaining opaque\. The model can discover useful addressable value structure, but that mechanism is not yet sufficient for the hardest held\-out temporal\-binding families\.

The spiking\-controller and closed\-loop control extensions test how far the same interface can be carried beyond supplied\-program execution\. The implemented spiking design confines spikes to the temporal controller state while keeping instruction encoding, the symbolicALUand writeback non\-spiking and inspectable\. This hybrid choice is important\.ALIFdynamics can represent event\-driven temporal memory, while arithmetic and destination writes remain named program operations\. The evidence supports feasibility, instrumentation and a device\-facing research route rather than superiority over the strongest non\-spiking executor\. On harder hidden\-memory programs, trace error grows with the temporal\-binding burden\. At the population level, mean spike rate alone does not explain control success\. The larger closed\-loop gains instead come from candidate\-constrained symbolic action search\. Candidate generation reduces the combinatorial operation, source and destination action space before policy scoring, which explains why the factorized MLP policies benefit most\. The residual oracle gap remains because the controller must still rank symbolic tuples under finite\-horizon rewards, while learned\-QAT8transition evaluation introduces approximation error into that ranking\.

The RV32I bridge sharpens the same architectural principle at a standardized instruction\-set boundary\. The difficult modes in that experiment, including trap state, JALR, load and store modes, held\-out sequences and length extrapolation, were not resolved by making the model less structured\. They were resolved by making the interface more architectural\. Decode, immediate reconstruction, PC update, memory access, x0 suppression and trap predicates are represented explicitly, while learned heads select among semantic\-control modes above that substrate\. Repeating the symbolic\-predicate controller across three seeds resolved the targeted weak modes, including 100% mode\-level accuracy for trap, JALR, load, store and memory\-trap decisions\. Program\-exact length extrapolation nevertheless remains below exact sequence execution\. This strengthens the central claim because it shows that the architecture can be coupled to a standardized base\-integer ISA substrate rather than only to synthetic symbolic opcodes\. It also defines a precise boundary for future work\. The reported RV32I result is a base\-integer semantic bridge with an official\-style signature harness\. It is not officialRISC\-Vcompliance, privileged execution, ABI/runtime support, M/A/C/F/D/V extension support or execution of arbitraryRISC\-Vbinaries by the main trained executor\.

Translation to physical implementation remains staged and testable\. The current device reference is an independent fixed\-point replay of destination writes\. It is not RTL, FPGA firmware, microcontroller code, neuromorphic hardware orRISC\-Vexecution\. Energy and delay remain dimensionless accounting proxies, while spike rates are averages of returned spike traces rather than measured event energy\. The next physical step is to export the implemented operation bank and low\-precision writeback semantics to a fixed\-point kernel, verify value\-level agreement against the matched replay, and then measure latency and energy on FPGA, microcontroller or neuromorphic hardware\. The most credible first demonstrator is a quantized symbolic coprocessor or controller module that proposes and verifies register\-state transitions, rather than a full general\-purpose CPU replacement\.

A broader industrial motivation is edge and embedded anomaly detection on constrained devices, where multivariate sensor streams must be monitored under tight latency, energy and interpretability constraints\. The present work does not evaluate a specific industrial deployment\. Its contribution is the inspectable, quantization\-simulated execution substrate on which a later anomaly\-detection controller could be built, tested under matched replay and validated through hardware\-in\-the\-loop experiments\.

Several limitations define the scope of these claims\. The teacher is a continuous register\-vector interpreter with named CPU\-like operations, not a bit\-exact integer instruction\-set emulator, and all training and evaluation programs are synthetic\. Quantization is simulated at the writeback boundary and verified against a matched fixed\-point replay\. We report no measured silicon energy, physical delay, physical fault injection or circuit\-noise validation, and the energy and delay figures remain dimensionless proxies\. The spiking\-controller and closed\-loop control experiments establish feasibility of the shared execution interface rather than superiority over the strongest non\-spiking executor, while autonomous control remains unsolved\. The RV32I result is a base\-integer semantic bridge and learned\-control diagnostic\. It is not officialRISC\-Vcompliance, privileged execution, ABI/runtime support or execution of arbitraryRISC\-Vbinaries\. More broadly, the contribution is not a general differentiable neural computer, neural algorithmic reasoner or program synthesizer\. It is a controlled register\-machine substrate in which learned execution can be checked step by step against reference semantics\.

In summary, a trace\-supervised symbolic neural CPU can execute controlled register\-machine programs while keeping the operation path, register trajectory and low\-precision writeback semantics open to inspection\. Under eight\-bit quantization\-simulated writeback, the symbolic operation path remains effectively exact through programs of 1,000 instructions\. The residual numerical drift arises from the continuous reference rather than from failure of the learned execution, and it vanishes under a matched fixed\-point replay\. The remaining boundaries involving hidden\-opcode memory pressure, the training\-horizon limit of the wider profile and the oracle gap in closed\-loop control define concrete next steps toward learned executors that are inspectable enough to be trusted\.

## 5Data and Code Availability

The source code, experiment configurations, plotting scripts and source\-data tables required to reproduce the reported figures and benchmark summaries are available from the corresponding author upon reasonable request\. The author will also deposit materials in the public GitHub repository[jseluis/symbolic\-neural\-cpu](https://github.com/jseluis/symbolic-neural-cpu)\. The repository will include the implementations, experiments configurations, evaluation scripts, figure\-generation scripts and derived source\-data tables used in this study\. No industrial field dataset is used in the present experiments\. Device\-facing deployment remains a future application direction\.

## 6Acknowledgements

This work was prepared as part of a broader research program on neuromorphic and quantized controllers for industrial anomaly detection\. The present article establishes the symbolic execution substrate\. Future work will address device\-facing anomaly detection and hardware\-in\-the\-loop deployment\. The research program from which this work emerged was initiated under the SNIC Small Compute projectArtificial Intelligence for Physics and Engineering: Modeling and Simulation, project No\. SNIC 2022/22\-843, conducted at Linköping University under the principal investigatorship of the author\[[47](https://arxiv.org/html/2607.10021#bib.bib70)\]\. That project established the broader research direction connecting artificial intelligence, graph neural networks, deep reinforcement learning, neuromorphic computing, and the modeling and simulation of physics and engineering systems\.

This work was supported by the Brazilian National Council for Scientific and Technological Development, CNPq, under grant No\. 445344/2024\-5\. The author acknowledges financial support through the Talentos Brasil Fellowship as Project Coordinator\. The author also acknowledges the Group of Artificial Intelligence in Applied Geophysics, GAIA, at the Federal University of Bahia, UFBA, for computational resources, research infrastructure and institutional support\.

## 7Author Contributions

J\.L\.L\.J\.S\. conceived the research direction, developed theSymbolic Neural CPUimplementation and benchmark suite, designed and executed the experiments, interpreted the results and prepared the manuscript\.

## 8Competing Interests

The author declares no competing interests\.

## Supplementary Information

### Supplementary figures

The supplementary figures provide the detailed diagnostics underlying the main figures\. Robustness, calibration, proxy\-cost, energy\-choice, architecture comparison and memory\-pressure analyses support[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3); their metric definitions follow[section˜2\.3](https://arxiv.org/html/2607.10021#S2.SS3)and TableLABEL:tab:notation\. The figures are organized around four checks: \(i\) how low\-precision replay changes reference semantics, \(ii\) whether the discrete operation path remains stable when soft confidence changes, \(iii\) which operations and timesteps carry residual error, \(iv\) and which harder task families require latent operation or memory\-use inference beyond visible\-opcode execution\. The controlled training\-horizon ablation \(Supplementary Fig\.[S16](https://arxiv.org/html/2607.10021#Sx1.F16)\) is the only supplementary comparison that required additional model training\.

![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_32wide_longhorizon.png)Supplementary Figure S1:Long\-horizon stability of the 32\-wide non\-QAT8extrapolation profile\.The 32\-wide continuous executor evaluated across program lengthsL∈\{20,…,1000\}L\\in\\\{20,\\dots,1000\\\}\. LengthsL<400L<400\(i\.e\.≤320\\leq 320\) reuse the single\-seed short/medium\-length benchmark grid \(numerically exact there, so they carry no across\-seed band\); lengthsL≥400L\\geq 400are the mean over three evaluation seeds×\\timeseight benchmark batches per length, with bands and bars showing across\-seed standard deviation\.\(a\)FinalMAE\\mathrm\{MAE\}\(solid\) and traceMAE\\mathrm\{MAE\}\(dashed\) on a logarithmic axis; exact \(zero\) values are drawn at a10−710^\{\-7\}display floor and the across\-seed band is shown only where the metric exceeds that floor\. Execution is exact throughL=400L\{=\}400; an endpoint\-only deviation appears atL=500L\{=\}500, after which finalMAE\\mathrm\{MAE\}saturates near44–5×10−25\\times 10^\{\-2\}while traceMAE\\mathrm\{MAE\}keeps growing, indicating progressive—no longer endpoint\-confined—trajectory drift beyond the training horizon\.\(b\)Faithfulness: gate\-path agreement drifts down from1\.01\.0to∼0\.97\{\\sim\}0\.97, whereas scalar\-grid\-exactness stays near90%90\\%throughout, showing that the degradation concentrates in a minority of off\-grid scalars rather than a global collapse of the opcode path\. This figure characterizes a training\-horizon extrapolation limit of this short\-horizon\-trained instance \(programs of at most 40 steps\)—removed by retraining the same architecture at a longer horizon \(Supplementary Fig\.[S16](https://arxiv.org/html/2607.10021#Sx1.F16)\)—rather than a limit of the wider state itself; the main\-text benchmark \([fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)\) uses the robust 16\-wideQAT8profile\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_width_scaling_comparison.png)Supplementary Figure S2:Width\-scaling diagnostics: 16\-wide target versus 32\-wide extrapolation\.The 16\-wide families of[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)together with the 32\-wide non\-QAT8profile, all on a matchedL∈\{20,…,1000\}L\\in\\\{20,\\dots,1000\\\}horizon\. “32\-wide dense” is the single\-seed dense run; “32\-wide extrapolation” is the multi\-seed sweep—two seeds atL≤320L\\leq 320and three seeds atL≥400L\\geq 400, so the across\-seed band \(standard deviation\) tightens at theL=320→400L\{=\}320\\to 400boundary as the seed count increases\.\(a,b\)Final\-state and traceMAE\\mathrm\{MAE\}\(log axis; exact values at the10−710^\{\-7\}floor\): 16\-wide non\-QAT8stays on the floor at every length, the 16\-wideQAT8families stay in the10−310^\{\-3\}band, and only the 32\-wide profile rises beyondL=500L\{=\}500\.\(c\)Scalar\-grid exactness:100%100\\%for 16\-wide non\-QAT8throughout and∼90%\{\\sim\}90\\%for 32\-wide beyondL=500L\{=\}500, while theQAT8families sit at2323–41%41\\%against the*continuous*reference \(matched replay is exact, Supplementary Fig\.[S7](https://arxiv.org/html/2607.10021#Sx1.F7)\)\.\(d\)Operation\-path \(gate\) agreement, axis zoomed to9090–102%102\\%: the long\-program ValueMemoryQAT8run holds100%100\\%, theQAT8family and the 32\-wide extrapolation run drift to∼97\{\\sim\}97–99%99\\%byL=1000L\{=\}1000, and even 16\-wide non\-QAT8dips to∼96%\{\\sim\}96\\%atL≥900L\\geq 900despite bit\-exact outputs \(output\-equivalent routing\)\.\(e\)Tolerance faithfulness at10−210^\{\-2\}:100%100\\%for 16\-wide non\-QAT8,∼56\{\\sim\}56–74%74\\%for theQAT8families,∼90%\{\\sim\}90\\%for 32\-wide beyondL=500L\{=\}500\. Means aggregate benchmark batches and available seeds\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_soft_hard_decoding_gap.png)Supplementary Figure S3:Soft\-to\-hard execution gap\.\(a\)Soft\-vs\-hard finalMAE\\mathrm\{MAE\}\(log axis\): the 16\-wide non\-QAT8andQAT8runs agree to∼10−4\{\\sim\}10^\{\-4\}throughL≈600L\{\\approx\}600and diverge to4\.2×10−44\.2\\times 10^\{\-4\}and2\.8×10−32\.8\\times 10^\{\-3\}byL=1000L\{=\}1000; the 32\-wide extrapolation run diverges sharply beyondL=400L\{=\}400; the long\-program ValueMemoryQAT8run is identical in both modes \(∼10−16\{\\sim\}10^\{\-16\}, at the floating\-point floor\)\.\(b\)Soft\-vs\-hard gate\-sequence agreement stays≥99\.9%\\geq 99\.9\\%for every profile and length, so the gap in \(a\) is entirely a continuous\-datapath effect, not a difference in opcode selection\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_gate_entropy_margin.png)Supplementary Figure S4:Gate confidence over length\.\(a\)Soft gate entropy and\(b\)top\-two gate margin versus program length\. Both are flat \(near\-zero entropy, unit margin\) throughL≈400L\{\\approx\}400, after which probability mass spreads\. The bit\-exact non\-QAT8run becomes the*least*soft\-confident atL=1000L\{=\}1000\(entropy0\.0400\.040, margin0\.9640\.964\), theQAT8family is intermediate \(entropy0\.0140\.014, margin0\.9880\.988\), and the long\-program ValueMemory run is essentially unaffected \(entropy∼2×10−6\{\\sim\}2\\times 10^\{\-6\}, margin1\.0001\.000\)\. The argmax decision, meaning the highest\-probability operation selected by the hard gate, is unchanged throughout \(cf\. Supplementary Fig\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)b\); only the probability*spread*grows\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_per_op_gate_calibration.png)Supplementary Figure S5:Length\-resolved per\-operation accuracy and calibration\.\(a\)Operation accuracy \(soft\-gate decoding\) and\(b\)calibration \(−log10⁡ECE\-\\log\_\{10\}\\mathrm\{ECE\}, whereECE\\mathrm\{ECE\}is expected calibration error\) summarized across the eight opcodes \(line: mean; band: 10–90th percentile across opcodes\) versus length, per profile\.\(c,d\)Per\-opcode heatmaps for the 16\-wideQAT8family: onlyADDloses accuracy at long lengths \(95\.7%95\.7\\%atL=1000L\{=\}1000\) and is the weakest\-calibrated row\.\(e,f\)Per\-opcode heatmaps for the 32\-wide extrapolation profile: the loss concentrates inMUL\(64\.0%64\.0\\%\) andSHR\(66\.5%66\.5\\%\) atL=1000L\{=\}1000, with the other opcodes near\-exact\. The long\-program ValueMemory track retains the highest calibration \(−log10⁡ECE≈8\-\\log\_\{10\}\\mathrm\{ECE\}\\approx 8\) at all lengths\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_trace_divergence_profile.png)Supplementary Figure S6:Trace\-divergence profile: where execution error accumulates within a program\.Per\-step hard traceMAE\\mathrm\{MAE\}versus normalized execution progress \(step/\(L−1\)/\(L\{\-\}1\)\)\.\(a\)Profile at each run’s longest available length \(16\-wide families and 32\-wide extrapolation atL=1000L\{=\}1000; 32\-wide dense atL=500L\{=\}500\): the 16\-wideQAT8families rise to a22–3×10−33\\times 10^\{\-3\}plateau within the first∼10%\{\\sim\}10\\%of execution and stay flat, the non\-QAT8run stays at the10−710^\{\-7\}floor \(exact at every step\), and the 32\-wide extrapolation run is at the floor for the first half before climbing to∼5×10−2\{\\sim\}5\\times 10^\{\-2\}\.\(b\)16\-wideQAT8family heatmap \(log10\\log\_\{10\}traceMAE\\mathrm\{MAE\}over progress×\\timeslength\): the early\-rising plateau is essentially length\-independent\.\(c\)32\-wide extrapolation heatmap: the high\-error boundary is diagonal because error onset is at a fixed absolute step \(≈494\{\\approx\}494\), i\.e\. at normalized progress494/L494/L\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure3.png)Supplementary Figure S7:Reference semantics forQAT8writeback \(full breakdown\)\.The matched\-replay recovery summarized in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d, reported here in full across all evaluation splits\.\(a\)Continuous\-reference final and traceMAE\\mathrm\{MAE\}over the extended length benchmark for theQAT8family and long\-program ValueMemoryQAT8run; shaded bands summarize available batches/runs\.\(b\)Split\-level error*magnitude*: the final\-state gap between continuous\-reference scoring and matched fixed\-point replay \(replay errors plotted at the numerical floor when zero\)\.\(c\)Split\-level program*pass\-rate*: faithfulness recovered by matched replay—continuous\-reference tolerance faithfulness declines on held\-out task/length splits, whereas matched replay exactness returns to 100% \(annotations show the recovered percentage points\); this panel is the source for[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)d\. Panels \(b\) and \(c\) are complementary views of the same five splits: \(b\) how large the continuous\-reference error is, \(c\) how many programs that error pushes outside tolerance\.\(d\)Dense\-benchmark distribution of continuous\-reference final and trace errors\. Matched replay gives zero final and traceMAE\\mathrm\{MAE\}and 100% scalar\-grid, tolerance and gate\-path faithfulness on all evaluated hard splits; the continuous drift is therefore a reference\-semantics mismatch rather than a breakdown of the quantization\-simulated replay\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure4.png)Supplementary Figure S8:Detailed robustness stress tests\.The perturbation curves underlying the robustness summary in[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)a\.\(a,b\)Final\-stateMAE\\mathrm\{MAE\}under input bit\-flip perturbation and least\-significant\-bit \(LSB\)\-scaled input noise, where LSB refers to the simulated input quantization scale rather than a physical circuit bit\.\(c,d\)Tolerance faithfulness under the same perturbations\. These are simulated model\-input perturbations applied during evaluation, not physical fault injection, radiation modelling or circuit\-level noise\. The corresponding main\-text panel reports the envelope: error rises and tolerance falls gradually rather than catastrophically\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure5.png)Supplementary Figure S9:Aggregate gate\-calibration diagnostic\.Calibration summary for the gate router on the ordinary benchmark\. The hard argmax gate path is saturated, so this aggregate figure serves as a verification diagnostic rather than as a main\-text contrast\. The more informative length\-, width\- and opcode\-resolved calibration analyses are Supplementary Figs\.[S3](https://arxiv.org/html/2607.10021#Sx1.F3)–[S5](https://arxiv.org/html/2607.10021#Sx1.F5)\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure6.png)Supplementary Figure S10:Proxy cost and accuracy diagnostic\.Energy/delay proxy relation for the ordinary 16\-wide benchmark\. This panel is not a true Pareto frontier and is not interpreted as measured device energy or delay\. It documents the shared dimensionless proxy\-cost accounting; the main\-text cost result is instead the equivalent\-program choice experiment in[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)b and Table[5](https://arxiv.org/html/2607.10021#S3.T5)\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure7.png)Supplementary Figure S11:Detailed energy\-choice symbolic execution\.Full breakdown of the equivalent\-program benchmark summarized in[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)b\. The key reading is any\-valid, not canonical\-only, trace agreement: for task families where the lower\-cost program differs from the canonical trace, canonical\-path agreement can be low while any\-valid and min\-energy gate agreement remain 100%\. This detailed view reports task\-specific proxy\-energy savings and trace errors; saturated agreement cells are stated in the main text rather than used as main evidence\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure8.png)Supplementary Figure S12:Detailed architecture comparison benchmark\.Full architecture comparison on the standard shared synthetic\-CPU distribution\. Zero\-length bars indicate errors at the display floor, not missing data\. The transformer scratchpad has no operation\-gate trace by design, so gate agreement is not computed for that baseline\. Because most structured variants solve this baseline task distribution exactly, the main text uses this figure primarily to support two diagnostic controls: removing gate supervision degrades operation\-path interpretability, and the ungated scratchpad baseline loses trace faithfulness\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure9.png)Supplementary Figure S13:Aggregate hidden\-opcode memory\-pressure benchmark\.Full split\-level memory\-pressure diagnostic behind[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)c\. The benchmark masks opcode hints and tests memory\-mediated task families, so its low gate agreement is not in conflict with the near\-exact visible\-opcode gate\-path result in[fig\.˜2](https://arxiv.org/html/2607.10021#S3.F2)\. It measures a different mechanism: operation identity and delayed memory use must be inferred from register\-state transitions rather than read directly from the instruction vector\. ValueMemory improves state and trace errors in some splits, but the aggregate remains far from the visible\-opcode regime because latent memory induction is still underconstrained for held\-out task families\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/Figure10.png)Supplementary Figure S14:Task\-level hidden\-memory breakdown\.Per\-task decomposition of the memory\-pressure benchmark summarized in[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)d\. ValueMemory andQAT8ValueMemory improve stack\-style held\-out cases, where repeated local retrieval and update are useful, whereas long hidden\-memory reversal remains difficult across variants because it requires sustained temporal binding, latent operation inference and ordered delayed writes\. The task\-level contrast explains why the aggregate degradation is concentrated in specific temporal\-memory families rather than distributed uniformly across all memory tasks\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/figure11_snn_pilot.png)Supplementary Figure S15:Spiking\-controller extension\.\(a\)Hybrid controller pathway used by the implemented spiking variants: instruction and register information are encoded as deterministic current, the adaptive leaky integrate\-and\-fire \(ALIF\) controller supplies temporal hidden state, and the symbolicALUand memory/writeback path remain non\-spiking and auditable\.\(b\)Compact 8\-wide comparison between the non\-spiking GRU ValueMemory baseline and anALIFcontroller withK=4K\{=\}4micro\-steps; labels report gate agreement for theALIFrun\.\(c\)Held\-out memory\-pressure finalMAE\\mathrm\{MAE\}as a function of spike\-regularization weightλ\\lambdaand micro\-step countKK\.\(d\)Memory\-pressure comparison of final and traceMAE\\mathrm\{MAE\}for ValueMemory\-QAT8and selectedALIFvariants\. These panels characterize a neuromorphic\-controller extension; they are not a claim of measured event energy or superiority over the non\-spikingQAT8baseline\. Spike rates are averaged returned spike traces, not raw hardware event counts\.![Refer to caption](https://arxiv.org/html/2607.10021v1/figures/FigureS_t400_mechanism.png)Supplementary Figure S16:What sets the 32\-wide long\-horizon limit: a controlled training ablation\.Hard finalMAE\\mathrm\{MAE\}versus program length \(log axis; exact/zero values drawn at a10−710^\{\-7\}display floor\) for the identical 32\-wide non\-QAT8architecture retrained while varying one factor at a time \(numbers in Supplementary Table[S1](https://arxiv.org/html/2607.10021#Sx1.T1)\)\. The three short\-horizon configurations trained on programs of at most 40 steps—the baseline configuration, the512512\-memory\-slot variant and the4545\-epoch variant—peel off the floor beyondL≈500L\{\\approx\}500–700700, whereas training on longer programs \(up to 80 or 160 steps\) keeps execution bit\-exact throughL=1000L\{=\}1000\. Memory\-slot count is non\-monotonic \(the128128\-slot run stays exact\) and more epochs*worsen*the far\-horizon error, so the limit is governed by the training horizon, not state width, memory capacity or training duration\.
### Supplementary tables

Supplementary Table S1:What sets the 32\-wide long\-horizon limit: a controlled training ablation\.The identical 32\-wide non\-QAT8GRU–NTM symbolic executor \(width3232,1616registers, hidden state256256; fixed seed\) was retrained while varying one factor at a time—maximum training length, memory slots, or epochs—and benchmarked overL=20L\{=\}20–10001000\(88batches×64\\times\\,64\)\. “Exact through” is the largest length with mean hard finalMAE\\mathrm\{MAE\}exactly0\. Training horizon—not state width, memory capacity, or training duration—governs the limit: maximum training length≥80\{\\geq\}80removes it entirely, while more memory slots or more epochs at maximum training length4040do not\.
### Supplementary note 1: full operation semantics

For normalized vectorsx,y∈\[0,1\]Wx,y\\in\[0,1\]^\{W\}, the implemented reference operations are:

AND​\(x,y\)\\displaystyle\\mathrm\{AND\}\(x,y\)=clip​\(x⊙y,0,1\),\\displaystyle=\\mathrm\{clip\}\(x\\odot y,0,1\),\(157\)OR​\(x,y\)\\displaystyle\\mathrm\{OR\}\(x,y\)=max⁡\(x,y\),\\displaystyle=\\max\(x,y\),\(158\)XOR​\(x,y\)\\displaystyle\\mathrm\{XOR\}\(x,y\)=\|x−y\|,\\displaystyle=\|x\-y\|,\(159\)ADD​\(x,y\)\\displaystyle\\mathrm\{ADD\}\(x,y\)=clip​\(x\+y,0,1\),\\displaystyle=\\mathrm\{clip\}\(x\+y,0,1\),\(160\)SUB​\(x,y\)\\displaystyle\\mathrm\{SUB\}\(x,y\)=clip​\(x−y,0,1\),\\displaystyle=\\mathrm\{clip\}\(x\-y,0,1\),\(161\)SHL​\(x,y\)\\displaystyle\\mathrm\{SHL\}\(x,y\)=clip​\(2​x,0,1\),\\displaystyle=\\mathrm\{clip\}\(2x,0,1\),\(162\)SHR​\(x,y\)\\displaystyle\\mathrm\{SHR\}\(x,y\)=0\.5​x,\\displaystyle=0\.5x,\(163\)MUL​\(x,y\)\\displaystyle\\mathrm\{MUL\}\(x,y\)=clip​\(x⊙y,0,1\)\.\\displaystyle=\\mathrm\{clip\}\(x\\odot y,0,1\)\.\(164\)The neural model uses the same fixed operation bank and learns to select the correct operation gate\. The matched fixed\-point replay uses the same operations and quantizes destination writeback values to the same simulated low\-precision grid\. In this operation bank,ANDandMULare identical continuous maps\. They remain different labels for gate\-supervision analysis, but they do not yet implement distinct integer bitwise and arithmetic semantics\.

### Supplementary note 2: manuscript scope

This scope map separates the evidence reported in the article from the follow\-up directions it motivates\. The central evidence is symbolic execution and quantization\-simulated writeback under matched fixed\-point replay\. Architecture comparisons provide ablations, spiking controllers provide a device\-facing extension, candidate\-constrained action search provides the closed\-loop control result, and the RV32I base\-integer bridge provides a standardized\-ISA extension\. OfficialRISC\-Vcompliance, broaderRISC\-Vextensions, applied anomaly detection on constrained devices and hardware implementation are reserved for future studies\.

Table 2:Manuscript scope\.Evidence blocks are assigned to the main execution claim, supplementary analyses or future research directions\.Experiment blockRole in this manuscriptInterpretationImplementation and generated dataSymbolic neural CPU implementationReproducible basis for the reported experimentsTrace learningGate\-supervised executionPrimary evidence for interpretable executionLength generalizationLong\-program evaluationPrimary evidence for extrapolation within controlled tasksLow\-precision replayQAT8and simulated robustnessPrimary quantization\-simulated writeback evidenceCost\-aware executionDimensionless energy/delay proxies and energy choicePrimary evidence for cost\-aware symbolic executionArchitecture benchmarkArchitecture comparisonSupplementary architecture comparison and ablationsSpiking controllersEvent\-driven controller variantsDevice\-facing extension, not main claimClosed\-loop controllerActor\-critic symbolic controlSupplementary controller extensionRV32I base\-integer bridgeStandardized\-ISA extensionDeterministic RV32I semantic audit and learned\-control diagnostic; not officialRISC\-Vcompliance or arbitraryRISC\-Vbinary executionBroaderRISC\-Vextensions and runtimeFollow\-up processor/toolchain projectPrivileged modes, CSRs, interrupts, ABI/runtime behaviour and M/A/C/F/D/V extensions are outside the present articleCandidate action searchCandidate masking and beam evaluationControl extension built on the trace\-audited execution substrate
### Supplementary note 3: derivation of the gate\-supervised objective

The gate\-supervised objective can be viewed as a constrained maximum\-likelihood problem\. Letr1:Tr\_\{1:T\}be the reference trace ando1:To\_\{1:T\}the operation sequence\. A fully probabilistic model factorizes as

pθ​\(r1:T,o1:T∣x1:T,r0\)=∏t=1Tpθ​\(ot∣ht\)​pθ​\(rt∣rt−1,ot,ht\)\.p\_\{\\theta\}\(r\_\{1:T\},o\_\{1:T\}\\mid x\_\{1:T\},r\_\{0\}\)=\\prod\_\{t=1\}^\{T\}p\_\{\\theta\}\(o\_\{t\}\\mid h\_\{t\}\)p\_\{\\theta\}\(r\_\{t\}\\mid r\_\{t\-1\},o\_\{t\},h\_\{t\}\)\.\(165\)Assuming a Laplace observation model for registers,

pθ​\(rt∣rt−1,ot,ht\)∝exp⁡\(−1σ​‖r^t−rt‖1\),p\_\{\\theta\}\(r\_\{t\}\\mid r\_\{t\-1\},o\_\{t\},h\_\{t\}\)\\propto\\exp\\left\(\-\\frac\{1\}\{\\sigma\}\\\|\\hat\{r\}\_\{t\}\-r\_\{t\}\\\|\_\{1\}\\right\),\(166\)and a categorical model for operations,

pθ​\(ot=k∣ht\)=πt,k,p\_\{\\theta\}\(o\_\{t\}=k\\mid h\_\{t\}\)=\\pi\_\{t,k\},\(167\)the negative log\-likelihood is proportional to

∑t‖r^t−rt‖1−σ​∑tlog⁡πt,ot\.\\sum\_\{t\}\\\|\\hat\{r\}\_\{t\}\-r\_\{t\}\\\|\_\{1\}\-\\sigma\\sum\_\{t\}\\log\\pi\_\{t,o\_\{t\}\}\.\(168\)The implemented loss is a weighted and regularized version of this objective, with an additional final\-state term to emphasize endpoint correctness and entropy/smoothness terms to improve optimization\. Thus gate supervision is not an arbitrary auxiliary loss\. It is the categorical part of the likelihood for the symbolic execution path\.

### Supplementary note 4: why energy\-choice tasks are necessary

Passive energy reporting is insufficient for a physics\-aware execution claim\. If a benchmark contains only one valid program for each target state, then energy is a label attached to the path, not a decision variable\. Equivalent\-program tasks create at least two paths:

x\(1\)≠x\(2\),𝒯​\(r0,x\(1\)\)=𝒯​\(r0,x\(2\)\),E​\(x\(1\)\)≠E​\(x\(2\)\)\.x^\{\(1\)\}\\neq x^\{\(2\)\},\\qquad\\mathcal\{T\}\(r\_\{0\},x^\{\(1\)\}\)=\\mathcal\{T\}\(r\_\{0\},x^\{\(2\)\}\),\\qquad E\(x^\{\(1\)\}\)\\neq E\(x^\{\(2\)\}\)\.\(169\)Only then can the model be tested for cost\-aware symbolic execution\. The min\-energy policy solves

x⋆=arg​minx∈𝒳​\(r0,rT\)​E​\(x\)subject​to𝒯​\(r0,x\)=rT\.x^\{\\star\}=\\mathrm\{arg\\,min\}\_\{x\\in\\mathcal\{X\}\(r\_\{0\},r\_\{T\}\)\}E\(x\)\\quad\\mathrm\{subject\\ to\}\\quad\\mathcal\{T\}\(r\_\{0\},x\)=r\_\{T\}\.\(170\)The implementation uses constructed equivalent families rather than a general compiler optimizer\. This demonstrates the principle under controlled conditions while leaving general program optimization for future work\.

### Supplementary note 5: real\-device pathway

The simulation\-to\-device pathway is staged\. First, export the trainedQAT8executor as fixed\-point kernels with explicit scales and clipping ranges matching theQBQ\_\{B\}projection\. Second, validate agreement between the matched fixed\-point replay and the exported implementation\. Third, deploy the kernel to an FPGA, microcontroller\-class accelerator or neuromorphic co\-processor interface\. Fourth, replace proxy energy with measured switching, latency and power\. Fifth, close the loop with hardware\-in\-the\-loop tests\.

The most plausible first physical demonstrator is not a general\-purpose CPU\. It is a symbolic neural co\-processor with a compact instruction vocabulary, fixed\-point register state and auditable operation gates\. Such a demonstrator can be useful for edge controllers, sensor\-state machines and anomaly\-detection front\-ends before it attempts richer instruction\-set compatibility\.

### Supplementary note 6: interpretation of saturated and contrasting metrics

##### Controlled execution distribution\.

The main distribution is controlled so that exact trace supervision, named operation labels and matched fixed\-point replay can be computed without ambiguity\. This design is necessary for a strict audit of execution: each active timestep has a reference register state, a reference opcode, a destination register and a low\-precision replay reference\. The harder task\-family and memory\-pressure benchmarks are therefore not replacements for the main distribution; they are contrastive tests that remove or perturb specific cues after the visible\-opcode executor has been established\.

##### Visible\-opcode and hidden\-opcode regimes\.

The main length benchmark evaluates visible\-opcode symbolic execution, whereas[fig\.˜3](https://arxiv.org/html/2607.10021#S3.F3)combines input perturbations, equivalent\-program choices, architecture ablations and hidden\-opcode memory tasks\. Exact operation paths on visible\-opcode programs are compatible with low gate agreement on hidden\-opcode memory\-pressure tasks because the latter removes the opcode one\-hot cue and requires the model to infer the operation family from register\-state transitions, delayed memory use and address\-dependent writes\. The mechanism is therefore not a contradiction between figures: it is a change in available information\. In visible\-opcode execution the router can condition directly on the encoded operation hint; in hidden\-opcode memory pressure the same router must infer the operation identity and memory\-access pattern from context, which is underconstrained for long hidden reversals and stack\-like updates\.

##### Cross\-benchmark signature\.

The cross\-benchmark signature is a compact visual index of benchmark axes, not a universal scalar ranking\. State and trace entries are measuredMAE\\mathrm\{MAE\}values; gate\-path loss is11minus gate agreement; tolerance loss is11minus tolerance faithfulness; and cost saving is a positive energy\-proxy reduction\. Blank cells indicate metrics that are not defined by the corresponding benchmark protocol\. The scratchpad row has no gate\-path value because the baseline does not expose the named operation\-gate trace used by the structured executor\. This distinction matters: scratchpad models can imitate endpoints, but they do not provide the operation\-level audit trail that defines the symbolic Neural CPU evaluation\.

##### Trace supervision and output imitation\.

The executor is not evaluated only as an input–output approximator\. Training includes final\-state, trace and categorical operation\-gate objectives, and evaluation reports full register trajectories and operation\-path agreement\. Removing gate supervision leaves the state and trace losses active, so the model can still learn some value updates, but the operation logits become weakly constrained by endpoint imitation alone\. This explains the NoGateLoss pattern: the benchmark does not collapse into random output, yet operation\-path agreement drops because the categorical likelihood term for the symbolic path has been removed\.

##### Low\-precision reference semantics\.

Continuous\-reference drift appears underQAT8because the executor writes back on an 8\-bit scalar grid while the reference trajectory is continuous\. Matched fixed\-point replay changes the reference to the same writeback semantics and recovers exact final and trace agreement on the relevant splits\. This is the appropriate simulation comparison before hardware export: it verifies that the learned executor follows its own low\-precision symbolic semantics, while not claiming integer\-only deployment, measured power or cycle\-accurate hardware timing\.

##### Proxy energy and spiking controllers\.

Energy and delay values are dimensionless simulation proxies derived from operation tables and program length, not physical measurements\. They are used to test whether equivalent\-program tasks can induce lower\-proxy\-cost valid execution, not to claim measured silicon savings\. Likewise, the spiking controllers are a device\-facing architectural extension: they replace the recurrent controller state with LIF/ALIF spike dynamics while keeping the symbolic ALU and memory path non\-spiking\. The SNN results support an inspectable neuromorphic research pathway, but they do not supersede the non\-spikingQAT8executor on memory\-pressure benchmarks\.

##### Closed\-loop control\.

Candidate\-constrained control improves success by narrowing the combinatorial symbolic action space before reinforcement learning chooses executable instructions\. The residual oracle gap remains because the learned controller must still rank candidate operations, source registers and destinations under finite\-horizon rewards and, in the learned\-transition setting, under approximation error from theQAT8transition model\. The control results are therefore an extension of the learned execution substrate rather than the core evidence for trace\-faithful symbolic execution\.

### Supplementary note 7: future device and industrial application pathway

Edge and embedded anomaly detection on constrained devices is a motivating application direction\. No industrial field dataset is included in this manuscript, and no anomaly\-detection result is claimed\. The present article is focused on implemented trace\-supervised symbolic execution, quantization\-simulated writeback under matched fixed\-point replay, architecture comparison ablations, energy\-choice execution, memory\-pressure limits, spiking\-controller extensions and candidate\-constrained control\. A later applied study can test whether this substrate improves anomaly detection on real multivariate sensor streams under device latency, energy and interpretability constraints\.

The future device route is similarly staged\. The present work provides fixed\-width register states, auditable operation gates, quantization\-simulatedALUor writeback execution and proxy costs\. A hardware study would need exported fixed\-point kernels, agreement against the matched replay, hardware\-in\-the\-loop validation and measured latency/energy\. These steps are outside the present results and are framed as the next research layer rather than as claims of this article\.

### Supplementary note 8: notation reference

This notation table is included to keep the main text readable while preserving strict mathematical consistency for implementation\-oriented readers\.

Table 3:Notation used in the manuscript\.SymbolMeaningWWRegister\-vector width used by the profile; implemented as a continuous vector dimension, not a packed integer word\.RRNumber of registers\.DRD\_\{R\}Guarded instruction\-index denominator,DR=max⁡\(1,R−1\)D\_\{R\}=\\max\(1,R\-1\), matching the implementation\.rt,r^tr\_\{t\},\\hat\{r\}\_\{t\}Reference and predicted register files at program steptt\.xtx\_\{t\}Encoded instruction containing one\-hot opcode and normalized source/destination register indices\.ξt\\xi\_\{t\}Symbolic instruction tuple\(ot,it,jt,dt\)\(o\_\{t\},i\_\{t\},j\_\{t\},d\_\{t\}\)before numeric encoding\.oto\_\{t\}Symbolic operation label at steptt\.it,jt,dti\_\{t\},j\_\{t\},d\_\{t\}Zero\-based source\-register and destination\-register indices\.ut,vtu\_\{t\},v\_\{t\}Operand vectors read from registersiti\_\{t\}andjtj\_\{t\}\.AkA\_\{k\}Implemented continuous operation proxy for operation labelkk\.πt\\pi\_\{t\}Learned gate distribution over symbolic operations\.mtm\_\{t\}Binary valid\-step or padding mask\.MtM\_\{t\}Differentiable NTM\-style memory state\.VtV\_\{t\}ValueMemory state used by the value\-memory variant\.QBQ\_\{B\}Uniform quantization\-simulatedALUor writeback projection withBBbits\.NBN\_\{B\}Mini\-batch size; distinct from quantization bit depthBB\.BbeamB\_\{\\mathrm\{beam\}\}Beam width in candidate\-control evaluation\.E,ΔE,\\DeltaDimensionless simulation proxy energy and delay, not physical measurements\.zt,kz\_\{t,k\}SNN spike state at micro\-stepkkinside program steptt\.𝒞​\(s\)\\mathcal\{C\}\(s\)Candidate action set for controller statess\.

## References

- \[1\]\(2025\)FeNN: a RISC\-V vector processor for spiking neural network acceleration\.Note:Accepted in Proceedings of Neuro Inspired Computational Elements Conference 2025External Links:2506\.11760,[Document](https://dx.doi.org/10.48550/arXiv.2506.11760),[Link](https://arxiv.org/abs/2506.11760)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p8.1)\.
- \[2\]D\. Bahdanau, K\. Cho, and Y\. Bengio\(2015\)Neural machine translation by jointly learning to align and translate\.arXiv preprint arXiv:1409\.0473\.External Links:1409\.0473Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p2.1)\.
- \[3\]S\. Bai, J\. Z\. Kolter, and V\. Koltun\(2018\)An empirical evaluation of generic convolutional and recurrent networks for sequence modeling\.arXiv preprint arXiv:1803\.01271\.Cited by:[§2\.8\.3](https://arxiv.org/html/2607.10021#S2.SS8.SSS3.p1.4)\.
- \[4\]P\. W\. Battaglia, J\. B\. Hamrick, V\. Bapst, A\. Sanchez\-Gonzalez, V\. Zambaldi, M\. Malinowski, A\. Tacchetti, D\. Raposo, A\. Santoro, R\. Faulkner, C\. Gulcehre, F\. Song, A\. Ballard, J\. Gilmer, G\. Dahl, A\. Vaswani, K\. Allen, C\. Nash, V\. Langston, C\. Dyer, N\. Heess, D\. Wierstra, P\. Kohli, M\. Botvinick, O\. Vinyals, Y\. Li, and R\. Pascanu\(2018\)Relational inductive biases, deep learning, and graph networks\.arXiv preprint arXiv:1806\.01261\.Cited by:[§2\.8\.3](https://arxiv.org/html/2607.10021#S2.SS8.SSS3.p1.4)\.
- \[5\]W\. Bounsi, B\. Ibarz, A\. Dudzik, J\. B\. Hamrick, L\. Markeeva, A\. Vitvitskyi, R\. Pascanu, and P\. Veličković\(2024\)Transformers meet neural algorithmic reasoners\.External Links:2406\.09308,[Link](https://arxiv.org/abs/2406.09308)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[6\]G\. W\. Brier\(1950\)Verification of forecasts expressed in terms of probability\.Monthly Weather Review78\(1\),pp\. 1–3\.Cited by:[§3\.2](https://arxiv.org/html/2607.10021#S3.SS2.p8.31)\.
- \[7\]K\. Cho, B\. van Merriënboer, C\. Gulcehre, D\. Bahdanau, F\. Bougares, H\. Schwenk, and Y\. Bengio\(2014\)Learning phrase representations using RNN encoder–decoder for statistical machine translation\.Proceedings of EMNLP,pp\. 1724–1734\.Cited by:[§2\.8\.3](https://arxiv.org/html/2607.10021#S2.SS8.SSS3.p1.2)\.
- \[8\]T\. H\. Cormen, C\. E\. Leiserson, R\. L\. Rivest, and C\. Stein\(2009\)Introduction to algorithms\.3 edition,MIT Press\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[9\]M\. Courbariaux, Y\. Bengio, and J\. David\(2015\)BinaryConnect: training deep neural networks with binary weights during propagations\.Advances in Neural Information Processing Systems28\.Note:arXiv:1511\.00363Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p8.2)\.
- \[10\]M\. Davies, A\. Wild, G\. Orchard, Y\. Sandamirskaya, G\. A\. F\. Guerra, P\. Joshi, P\. Plank, and S\. R\. Risbud\(2021\)Advancing neuromorphic computing with Loihi: a survey of results and outlook\.Proceedings of the IEEE109\(5\),pp\. 911–934\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p8.1)\.
- \[11\]S\. K\. Esser, J\. L\. McKinstry, D\. Bablani, R\. Appuswamy, and D\. S\. Modha\(2020\)Learned step size quantization\.International Conference on Learning Representations\.Note:arXiv:1902\.08153Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p8.2)\.
- \[12\]A\. Graves, A\. Mohamed, and G\. Hinton\(2013\)Speech recognition with deep recurrent neural networks\.2013 IEEE International Conference on Acoustics, Speech and Signal Processing,pp\. 6645–6649\.External Links:[Document](https://dx.doi.org/10.1109/ICASSP.2013.6638947)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p2.1)\.
- \[13\]A\. Graves, G\. Wayne, and I\. Danihelka\(2014\)Neural turing machines\.arXiv preprint arXiv:1410\.5401\.External Links:1410\.5401Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p3.1),[§2\.8\.7](https://arxiv.org/html/2607.10021#S2.SS8.SSS7.p1.5)\.
- \[14\]A\. Graves, G\. Wayne, M\. Reynolds, T\. Harley, I\. Danihelka, A\. Grabska\-Barwińska, S\. G\. Colmenarejo, E\. Grefenstette, T\. Ramalho, J\. Agapiou, A\. P\. Badia, K\. M\. Hermann, Y\. Zwols, G\. Ostrovski, A\. Cain, H\. King, C\. Summerfield, P\. Blunsom, K\. Kavukcuoglu, and D\. Hassabis\(2016\)Hybrid computing using a neural network with dynamic external memory\.Nature538,pp\. 471–476\.External Links:[Document](https://dx.doi.org/10.1038/nature20101)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p1.1),[§1](https://arxiv.org/html/2607.10021#S1.p3.1),[§2\.8\.7](https://arxiv.org/html/2607.10021#S2.SS8.SSS7.p1.5)\.
- \[15\]A\. Graves\(2013\)Generating sequences with recurrent neural networks\.arXiv preprint arXiv:1308\.0850\.External Links:1308\.0850Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p2.1)\.
- \[16\]A\. Gu, K\. Goel, and C\. Ré\(2022\)Efficiently modeling long sequences with structured state spaces\.International Conference on Learning Representations\.Cited by:[§2\.8\.3](https://arxiv.org/html/2607.10021#S2.SS8.SSS3.p1.4)\.
- \[17\]C\. Guo, G\. Pleiss, Y\. Sun, and K\. Q\. Weinberger\(2017\)On calibration of modern neural networks\.International Conference on Machine Learning,pp\. 1321–1330\.Cited by:[§3\.2](https://arxiv.org/html/2607.10021#S3.SS2.p8.31)\.
- \[18\]B\. Hashemi, K\. Pasque, C\. Teska, and R\. Yoshida\(2025\)Tropical attention: neural algorithmic reasoning for combinatorial algorithms\.External Links:2505\.17190,[Link](https://arxiv.org/abs/2505.17190)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[19\]Y\. He and E\. Vitercik\(2025\)Primal\-dual neural algorithmic reasoning\.External Links:2505\.24067,[Link](https://arxiv.org/abs/2505.24067)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[20\]S\. Hochreiter and J\. Schmidhuber\(1997\)Long short\-term memory\.Neural Computation9\(8\),pp\. 1735–1780\.External Links:[Document](https://dx.doi.org/10.1162/neco.1997.9.8.1735)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p2.1)\.
- \[21\]Q\. Hu, Q\. Long, and W\. Wang\(2026\)When continual learning moves to memory: a study of experience reuse in llm agents\.arXiv preprint arXiv:2604\.27003\.External Links:2604\.27003Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p6.1)\.
- \[22\]I\. Hubara, M\. Courbariaux, D\. Soudry, R\. El\-Yaniv, and Y\. Bengio\(2018\)Quantized neural networks: training neural networks with low precision weights and activations\.Journal of Machine Learning Research18\(187\),pp\. 1–30\.Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p8.2)\.
- \[23\]M\. E\. Isenkul\(2025\)Energy\-aware deep learning for real\-time video analysis through pruning, quantization, and hardware optimization\.Journal of Real\-Time Image Processing22\(125\)\.External Links:[Document](https://dx.doi.org/10.1007/s11554-025-01703-0)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p7.1)\.
- \[24\]B\. Jacob, S\. Kligys, B\. Chen, M\. Zhu, M\. Tang, A\. Howard, H\. Adam, and D\. Kalenichenko\(2018\)Quantization and training of neural networks for efficient integer\-arithmetic\-only inference\.Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition,pp\. 2704–2713\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p7.1)\.
- \[25\]E\. Jang, S\. Gu, and B\. Poole\(2017\)Categorical reparameterization with gumbel\-softmax\.International Conference on Learning Representations\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p11.4),[§2\.8\.4](https://arxiv.org/html/2607.10021#S2.SS8.SSS4.p3.1)\.
- \[26\]Ł\. Kaiser and I\. Sutskever\(2016\)Neural GPUs learn algorithms\.International Conference on Learning Representations\.Note:arXiv:1511\.08228Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p5.10)\.
- \[27\]T\. N\. Kipf and M\. Welling\(2017\)Semi\-supervised classification with graph convolutional networks\.International Conference on Learning Representations\.Cited by:[§2\.8\.3](https://arxiv.org/html/2607.10021#S2.SS8.SSS3.p1.4)\.
- \[28\]R\. Krishnamoorthi\(2018\)Quantizing deep convolutional networks for efficient inference: a whitepaper\.arXiv preprint arXiv:1806\.08342\.External Links:1806\.08342Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p7.1)\.
- \[29\]K\. Kurach, M\. Andrychowicz, and I\. Sutskever\(2016\)Neural random\-access machines\.International Conference on Learning Representations\.Note:arXiv:1511\.06392Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p5.10)\.
- \[30\]E\. La Malfa, C\. Weinhuber, O\. Torre, F\. Lin, X\. A\. Huang, S\. Marro, A\. Cohn, N\. Shadbolt, and M\. Wooldridge\(2025\)Code simulation as a proxy for high\-order tasks in large language models\.External Links:2502\.03568,[Link](https://arxiv.org/abs/2502.03568)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p5.1)\.
- \[31\]C\. Li, N\. Imam, and R\. Manohar\(2025\)A deterministic neuromorphic architecture with scalable time synchronization\.Nature Communications16\(10329\)\.External Links:[Document](https://dx.doi.org/10.1038/s41467-025-65268-z),[Link](https://www.nature.com/articles/s41467-025-65268-z)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p8.1)\.
- \[32\]H\. Li, C\. Peng, C\. Xu, and Z\. Yang\(2024\)Open\-book neural algorithmic reasoning\.Advances in Neural Information Processing Systems\.Note:arXiv:2501\.00072External Links:2501\.00072Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[33\]X\. Li, Y\. Liang, J\. Long, Z\. Shi, Z\. Song, and Z\. Zhuang\(2025\)Neural algorithmic reasoning for hypergraphs with looped transformers\.External Links:2501\.10688,[Link](https://arxiv.org/abs/2501.10688)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[34\]M\. Lin, Z\. Zhang, H\. Lu, H\. Liu, X\. Tang, Q\. He, X\. Zhang, and S\. Wang\(2026\)MemMA: coordinating the memory cycle through multi\-agent reasoning and in\-situ self\-evolution\.arXiv preprint arXiv:2603\.18718\.External Links:2603\.18718Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p6.1)\.
- \[35\]M\. V\. Macfarlane, C\. Bonnet, H\. van Hoof, and L\. H\. S\. Lelis\(2026\)Gradient\-based program synthesis with neurally interpreted languages\.External Links:2604\.18907,[Link](https://arxiv.org/abs/2604.18907)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p5.1)\.
- \[36\]C\. J\. Maddison, A\. Mnih, and Y\. W\. Teh\(2017\)The concrete distribution: a continuous relaxation of discrete random variables\.International Conference on Learning Representations\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p11.4),[§2\.8\.4](https://arxiv.org/html/2607.10021#S2.SS8.SSS4.p3.1)\.
- \[37\]V\. Mnih, A\. P\. Badia, M\. Mirza, A\. Graves, T\. Lillicrap, T\. Harley, D\. Silver, and K\. Kavukcuoglu\(2016\)Asynchronous methods for deep reinforcement learning\.International Conference on Machine Learning,pp\. 1928–1937\.Cited by:[§2\.7](https://arxiv.org/html/2607.10021#S2.SS7.p1.1)\.
- \[38\]L\. Mueller, A\. Garcia\-Ortiz, A\. Najafi, A\. Fuks, and L\. Bamberg\(2025\)Rescaling\-aware training for efficient deployment of deep learning models on full\-integer hardware\.External Links:2510\.11484,[Link](https://arxiv.org/abs/2510.11484)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p7.1),[§1](https://arxiv.org/html/2607.10021#S1.p8.1)\.
- \[39\]A\. Neelakantan, Q\. V\. Le, and I\. Sutskever\(2016\)Neural programmer: inducing latent programs with gradient descent\.International Conference on Learning Representations\.Note:arXiv:1511\.04834Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p5.10)\.
- \[40\]D\. A\. Patterson and J\. L\. Hennessy\(2020\)Computer organization and design risc\-v edition: the hardware software interface\.2 edition,Morgan Kaufmann\.External Links:ISBN 9780128203316Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p3.7)\.
- \[41\]G\. D\. Plotkin\(2004\)A structural approach to operational semantics\.The Journal of Logic and Algebraic Programming60–61,pp\. 17–139\.External Links:[Document](https://dx.doi.org/10.1016/j.jlap.2004.05.001)Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p1.1)\.
- \[42\]S\. Požgaj, D\. Georgiev, M\. Šilić, and P\. Veličković\(2025\)KNARsack: teaching neural algorithmic reasoners to solve pseudo\-polynomial problems\.External Links:2509\.15239,[Link](https://arxiv.org/abs/2509.15239)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[43\]M\. J\. Rasch, F\. Carta, O\. Fagbohungbe, and T\. Gokmen\(2024\)Fast and robust analog in\-memory deep neural network training\.Nature Communications15,pp\. 7133\.External Links:[Document](https://dx.doi.org/10.1038/s41467-024-51221-z)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p7.1),[§1](https://arxiv.org/html/2607.10021#S1.p8.1)\.
- \[44\]S\. Reed and N\. de Freitas\(2016\)Neural programmer\-interpreters\.International Conference on Learning Representations\.Note:arXiv:1511\.06279Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p5.10)\.
- \[45\]J\. Schulman, F\. Wolski, P\. Dhariwal, A\. Radford, and O\. Klimov\(2017\)Proximal policy optimization algorithms\.arXiv preprint arXiv:1707\.06347\.Cited by:[§2\.7](https://arxiv.org/html/2607.10021#S2.SS7.p1.1)\.
- \[46\]J\. C\. Shepherdson and H\. E\. Sturgis\(1963\)Computability of recursive functions\.Journal of the ACM10\(2\),pp\. 217–255\.External Links:[Document](https://dx.doi.org/10.1145/321160.321170)Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p1.1)\.
- \[47\]J\. L\. L\. d\. J\. Silva\(2022\)Artificial intelligence for physics and engineering: modeling and simulation\.Note:SNIC Small Compute Project, National Supercomputer Centre, Linköping UniversityProject No\. SNIC 2022/22\-843External Links:[Link](https://nim.nsc.liu.se/projects/4658/)Cited by:[§6](https://arxiv.org/html/2607.10021#S6.p1.1)\.
- \[48\]A\. Solko\-Breslin, S\. Choi, Z\. Li, N\. Velingker, R\. Alur, M\. Naik, and E\. Wong\(2024\)Data\-efficient learning with neural programs\.Advances in Neural Information Processing Systems\.External Links:2406\.06246Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p5.1)\.
- \[49\]S\. Sukhbaatar, J\. Weston, R\. Fergus,et al\.\(2015\)End\-to\-end memory networks\.Advances in Neural Information Processing Systems28\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p3.1)\.
- \[50\]I\. Sutskever, O\. Vinyals, and Q\. V\. Le\(2014\)Sequence to sequence learning with neural networks\.Advances in Neural Information Processing Systems27\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p2.1)\.
- \[51\]R\. S\. Sutton and A\. G\. Barto\(2018\)Reinforcement learning: an introduction\.2 edition,MIT Press\.Cited by:[§2\.7](https://arxiv.org/html/2607.10021#S2.SS7.p1.1)\.
- \[52\]B\. Tang and W\. Xie\(2026\)Transformers are stateless differentiable neural computers\.arXiv preprint arXiv:2603\.19272\.External Links:2603\.19272Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p3.1)\.
- \[53\]A\. M\. Turing\(1936\)On computable numbers, with an application to the entscheidungsproblem\.Proceedings of the London Mathematical Societys2\-42\(1\),pp\. 230–265\.External Links:[Document](https://dx.doi.org/10.1112/plms/s2-42.1.230)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p1.1)\.
- \[54\]Q\. Van Baelen and P\. Karsmakers\(2025\)Constraint guided model quantization of neural networks\.arXiv preprint arXiv:2409\.20138\.External Links:2409\.20138Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p7.1)\.
- \[55\]A\. Vaswani, N\. Shazeer, N\. Parmar, J\. Uszkoreit, L\. Jones, A\. N\. Gomez, Ł\. Kaiser, and I\. Polosukhin\(2017\)Attention is all you need\.Advances in Neural Information Processing Systems30\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p3.1),[§2\.8\.3](https://arxiv.org/html/2607.10021#S2.SS8.SSS3.p1.4)\.
- \[56\]P\. Veličković, A\. P\. Badia, D\. Budden, R\. Pascanu, A\. Banino, M\. Dashevskiy, R\. Hadsell, and C\. Blundell\(2022\)The clrs algorithmic reasoning benchmark\.Proceedings of the 39th International Conference on Machine Learning162,pp\. 22084–22102\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p4.1)\.
- \[57\]O\. Vinyals, M\. Fortunato, and N\. Jaitly\(2015\)Pointer networks\.Advances in Neural Information Processing Systems28\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p2.1)\.
- \[58\]J\. von Neumann\(1945\)First draft of a report on the edvac\.Technical reportMoore School of Electrical Engineering, University of Pennsylvania\.Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p1.1)\.
- \[59\]J\. Weston, S\. Chopra, and A\. Bordes\(2014\)Memory networks\.arXiv preprint arXiv:1410\.3916\.External Links:1410\.3916Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p3.1)\.
- \[60\]W\. Zaremba and I\. Sutskever\(2014\)Learning to execute\.arXiv preprint arXiv:1410\.4615\.External Links:1410\.4615Cited by:[§2\.1](https://arxiv.org/html/2607.10021#S2.SS1.p5.10)\.
- \[61\]M\. Zhuge, C\. Zhao, H\. Liu, Z\. Zhou, S\. Liu, W\. Wang, E\. Chang, G\. Le Lan, J\. Fei, W\. Zhang, Y\. Sun, Z\. Cai, Z\. Liu, Y\. Xiong, Y\. Yang, Y\. Tian, Y\. Shi, V\. Chandra, and J\. Schmidhuber\(2026\)Neural computers\.External Links:2604\.06425,[Document](https://dx.doi.org/10.48550/arXiv.2604.06425),[Link](https://arxiv.org/abs/2604.06425)Cited by:[§1](https://arxiv.org/html/2607.10021#S1.p8.1)\.