Apple M1 Chip Deep-Dive

### TL;DR The Apple M1 is a revolutionary SoC integrating 16 billion transistors, setting new benchmarks in performance and efficiency through clever die layout and on-package memory. ## From Product Design to Chip Design Apple has always been known for product design, but as early as 2010 with the A4 chip, it took its first step as a chip design company. Today, Apple Silicon is no longer just a marketing term—it's a success story. Unlike product design, the beauty of chip design is hidden inside iPhones or Macs and hard to see. Thanks to ultra-high-resolution die micrographs by Fritzchens Fritz, we can dive deep into the beautiful world of the M1. ## Dissecting the M1 Chip The micrographs in this video come from an M1 MacBook Air. The logic board was extracted from the chassis, the M1 package was desoldered, and the metal heat sink was removed. The M1 uses on-package memory, with two LPDDR4x DRAM modules next to the die on the same package. This reduces data travel distance, improves efficiency, and makes the overall design more compact. Next, the silicon die was stripped from the package substrate. An interesting discovery is that the M1 uses an "embedded silicon capacitor"—the tiny rectangular shapes visible in the image—which helps power the most critical parts of the chip. Finally, the entire silicon die was ground down layer by layer until the transistor structures were revealed. ## Technical Specifications The M1 is manufactured on TSMC's N5 process node, containing approximately 16 billion transistors on a 120.4 mm² die (increasing to 123.14 mm² when including the scribe lines). As an SoC, it integrates: - 8-core CPU (4 performance cores + 4 efficiency cores) - 8-core GPU - 16-core NPU - System-Level Cache (SLC) - 128-bit memory interface - Extensive I/O (including Thunderbolt) - Media engine and display engine - Digital signal processor and image signal processor ## Die Analysis Strategy High-resolution micrographs inspire awe and confusion. Even for experienced analysts, it takes time to digest—we're looking at a picture drawn by 16 billion transistors. A single pixel may contain thousands of transistors. To analyze, start from the chip's "coastline" (edges), where all components that communicate with the outside world are placed: memory interfaces and I/O blocks. Any analysis involves some degree of uncertainty. ### Memory Interface The memory interface is visible along the top-left, top, and right coastlines. There are eight 16-bit memory PHYs, combined into a 128-bit wide memory interface. Apple's memory architecture is very space-efficient, tightly integrating memory control functions with the PHY. The PHY provides the physical points of contact extending to the on-package DRAM. ### I/O Coastline Continuing down the coastline, a Display Port PHY can be found in the bottom-left corner of the die, adjacent to Thunderbolt logic. Two Thunderbolt 3 ports are split into two control areas and two PHYs. The control area also includes a standard USB logic block, adding USB4 functionality to the port. Next is the PCI-Express area, offering five physical lanes. PCIe is used to connect Wi-Fi/Bluetooth modules, handle Ethernet on Mac mini or iMac, and for tunneling support. Thunderbolt and PCIe PHYs share the same physical implementation because both use high-speed SerDes (serializer/deserializer); Apple uses the same SerDes design for both. To the right of the PCIe area is a separate, smaller USB PHY, followed by a more significant region—Apple's proprietary NAND storage controller (ANS). Unlike other companies, Apple's SSDs contain only raw NAND chips because the storage controller is on the SoC. The ANS includes about 3.5 MB of fast SRAM (for buffering and data stream sequencing) and an eFuse that holds storage encryption keys. Instant encryption also requires a dedicated AES engine, so the ANS is tightly linked to on-board security logic. Directly beneath the ANS controller, you can see that Apple does not use PCIe to connect SSDs but instead uses a parallel dual-channel NAND architecture, totaling 92 visible I/O pads. This is direct parallel storage access, one reason Apple's SSDs are extremely fast (if enough NAND chips are used to saturate the dual-channel interface). ### The Unusually Large PHY Cluster The large PHY cluster next to the NAND controller is very special—this is Apple's proprietary camera interface. It is not for webcams but for large, high-resolution camera clusters like those in iPhones or iPads. The M1 iPad Pro is the only M1 product that uses this PHY; on all other M1 devices (MacBook Air/Pro, Mac mini, iMac), this area is inactive. Apple implemented this PHY for a single product. Webcams on MacBooks or iMacs connect via a tiny MIPI D-PHY at the top-right corner of the die, which also reads the infrared camera used for Face ID (on M1 iPad Pro). ## Internal Major IP Blocks ### GPU The GPU block is approximately 23.26 mm², the largest area on the M1. From the top-left to the center of the die, eight GPU cores are connected by shared control logic. A single GPU core is about 2.48 mm². In some binned parts, one GPU core is disabled (via a small cluster of eFuses at the far left of the GPU). ### System-Level Cache (SLC) The SLC is located directly below the GPU, serving as the last-level cache for the entire system. It is equally accessible to the CPU, GPU, NPU, etc. It is the central data structure hub connecting the whole chip. The M1's SLC totals 8 MB of SRAM, divided into four 2 MB sections. 1 MB of SRAM occupies approximately 0.28 mm². ### CPU P-Core (Firestorm) The large P-core cluster is to the left of the SLC, containing four Firestorm performance cores (two above, two below) with a shared L2 cache in the center. A single Firestorm core is about 2.25 mm². The P-cores are based on the ARMv8 architecture, but Apple has long developed internal ISA extensions, and Apple Silicon is increasingly transitioning to a unique version of the underlying ARM RISC architecture. The shared P-core L2 cache totals 12 MB (larger than the SLC). The P-core cluster also includes a dedicated AMX unit (matrix accelerator) for AI computation. The total area of the P-core cluster is 15.42 mm², second only to the GPU. ### CPU E-Core (Icestorm) The E-core cluster also contains four cores, but the Icestorm E-cores are very small, each only 0.6 mm². All four E-cores share a 4 MB L2 cache and also have their own AMX unit. The total E-core cluster size is 5.3 mm², nearly three times smaller than the P-core cluster. ### NPU (Apple Neural Engine) The NPU sits between the P-cores and E-cores, easily identifiable by its striking layout. All 16 cores are clearly visible, surrounding a shared scratchpad RAM. A single NPU core is only 0.21 mm². ## Unlabeled Areas Besides the major functional blocks mentioned, there are many unlabeled areas on the die. They include: the display composition engine (driving display output), the media engine (with dedicated encode/decode engines, though M1 does not support ProRes), the image signal processor and digital signal processor, a general-purpose I/O root hub, and extensive datapath logic. Some speculation points to a large mirrored cluster adjacent to the GPU in the top-right corner possibly containing the display composition engine; audio processing also happens in that area. Further down could be the image signal processor and video codec region. These labels are based on more or less educated guesses, and different analysts may reach different conclusions. By comparing die micrographs of M1 Pro/Max, or looking at real-time thermal maps of the chip when testing specific functions, each module can be identified more clearly. ## Conclusion The Apple M1 is a revolution. It not only shows that Apple can design laptop-class chips but also surpasses competitors in performance and efficiency. The M1 made Apple Silicon the gold standard, expanding Apple's image from a product design company to a chip design giant. Subsequent M-series generations have further cemented this position, and now Apple Silicon itself is a brand, part of Apple's identity. This article is based on die micrographs provided by Fritzchens Fritz and is the first in a series of deep dives into Apple Silicon chips. **Source: Apple M1 Chip Deep-Dive (https://www.youtube.com/watch?v=mHEWMiHgyU8)**