Alibaba's RISC-V CPU, XuanTie C950, Runs Qwen-3.8 27B at 30 tps

# Alibaba’s TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds Source: [https://wccftech.com/alibabas-tsmc-built-5nm-risc-v-chip-xuantie-c950-now-runs-qwen-3-8-27b-model-natively-unlocking-massive-vertical-integration-tailwinds/](https://wccftech.com/alibabas-tsmc-built-5nm-risc-v-chip-xuantie-c950-now-runs-qwen-3-8-27b-model-natively-unlocking-massive-vertical-integration-tailwinds/) Alibaba appears to be emulating NVIDIA's well\-established vertical integration playbook by bringing day\-zero support for its highly capable Qwen\-3\.8 27B AI model \- one that can run on just[32GB of VRAM](https://x.com/tphuang/status/2089551401084944622)\- to its bespoke RISC\-V chip, called XuanTie C950\. ## Alibaba can now run its Qwen\-series AI models on its own chips, carving out a hefty moat for itself in one of the world's most competitive AI markets [](https://cdn.wccftech.com/wp-content/uploads/2026/08/XuanTie-C950-Architecture-1.jpg)[Source](https://circuitdigest.com/news/alibaba-unveiled-xuantie-c950-high-performance-risc-v-core-for-edge-ai)Alibaba unveiled the XuanTie C950 in March 2026, marketing the chip as a RISC\-V\-based offering for edge AI\. Unlike typical ASICs, the XuanTie C950 does not rely on GPUs for AI workloads\. Instead, the chip is basically a server\-grade 64\-bit RISC\-V processor, replete with 64 compute cores located on a single piece of silicon, with clock frequencies that are scalable up to 3\.20GHz, and where multiple clusters \- 8 cores per cluster \- are linked together natively using high\-speed AMBA CHI fabrics\. What's more, to handle demanding AI workloads,[matrix and vector acceleration engines are embedded directly into the chip](https://circuitdigest.com/news/alibaba-unveiled-xuantie-c950-high-performance-risc-v-core-for-edge-ai), eliminating the need for GPUs\. Alibaba's XuanTie C950 features standard L1 caches, a flexible and highly configurable L2 cache, and supports an optional shared L3 cache to prevent inter\-core communication bottlenecks\. The chip also utilizes hardware\-level intelligent data prefetching algorithms to load memory strings into the cache hierarchy before the execution engine requests them\. Other important details include: 1. The chip is based on the open\-source RISC\-V ISA, which allows Alibaba to bypass licensing fees associated with the x86 architecture or ARM's designs\. This also allows for greater customization\. 2. The chip utilizes an 8\-instruction decode width, allowing the core to read and process a large volume of commands simultaneously\. 3. The chip features a 16\-stage pipeline, which strikes a balance between maintaining high clock speeds and efficiently executing complex server and AI workloads by breaking down each instruction into 16 parts\. 4. Unlike GPUs, the XuanTie C950 runs a single inference thread per socket, making it better suited for edge deployment and private inference rather than high\-concurrency public APIs\. 5. The combination of the custom pipeline and the integrated acceleration engines makes the XuanTie C950 the first RISC\-V processor designed to run billion\-parameter Large Language Models \(LLMs\) completely natively, and without the need for emulation or translation layers \- the hardware units and instruction set extensions are designed to directly execute the core operations required by small\- and medium\-sized AI models\. 6. Critically, the XuanTie C950 is[believed to be fabricated by TSMC on its 5nm node](https://www.trendforce.com/news/2026/03/25/news-alibaba-unveils-risc-v-xuantie-c950-cpu-for-ai-agents-5nm-chip-reportedly-made-by-tsmc/), though Alibaba has issued no direct confirmation\. > Alibaba T\-Head's Xuantie RISC\-V team announces Day 0 support for Qwen\-3\.8 model, especially the 27B one\. Its 64\-core C950 CPU \(w/ RVV support\) can decode at 30 tps w/ 1\.9s TTFT\. Xuantie family has wide series of RISC\-V chips for different edge applications\. Ali can now sell the…[https://t\.co/yF731bykS1](https://t.co/yF731bykS1)[pic\.twitter\.com/qmHfiZBxpa](https://t.co/qmHfiZBxpa) — tphuang \(@tphuang\)[August 18, 2026](https://x.com/tphuang/status/2089695207692312788?ref_src=twsrc%5Etfw) This brings us to the core of today's topic\. Alibaba has now brought day\-zero support for its latest Qwen\-3\.8 27B model to the XuanTie C950 chip, offering decode speeds of 30 tokens per second, and a Time To First Token \(TTFT\) of just 1\.9 seconds\. For the benefit of those who might not be aware, the[Qwen\-3\.8 27B](https://wccftech.com/deepseeks-peak-hour-pricing-betrays-where-its-users-really-live-calming-us-fears-of-a-china-ai-takeover-even-as-alibabas-qwen-models-bury-meta-on-hugging-face/)is a 27\-billion\-parameter open\-weight AI model that sports coding capabilities that are similar to Opus 4\.5, and yet can run on a single MacBook\.   By bringing day\-zero support for this model to the XuanTie C950, Alibaba is not only trying to lock customers within its own ecosystem but also substantially expanding the optionality around its compute footprint\. After all, Alibaba can easily pair the C950 with other AI accelerators within its data centers to efficiently handle inference\-related workloads\. [](https://wccftech.com/author/rohail/) **About the[author](https://wccftech.com/author/rohail/):**Writing is my one incontrovertible passion\. Over the past six years, he has authored over 2,200 distinct articles on financial and tech\-related topics, spanning nearly 1 million words\. And he has been a member of Wcctech[mobile](https://wccftech.com/topic/gadgets/)team since 2025\. As an alumnus of the University of Toronto, Rotman Commerce Program, I bring nuance, in\-depth knowledge, and a unique perspective to every topic that I cover\. When I'm not writing, I'm traveling the world, exploring hidden confectionaries and restaurants as an aspiring food connoisseur\. Follow[Wccftech on Google](https://profile.google.com/cp/Cg0vZy8xMWM3NDB2MmIyGgA)to get more of our news coverage in your feeds\.