asic

This article provides a solution to Jane Street's ASIC reverse engineering puzzle, detailing the process of analyzing GDS files and inferring the circuit using the SkyWater 130 nm standard-cell library documentation.

The author details their month-long effort to solve Jane Street's reverse engineering challenge for an ASIC chip, describing the technical process of analyzing GDS files and building custom simulation tools.

An analysis of AI inference hardware, comparing Taalas and Groq's approaches to etching model weights into silicon, and noting recent investments by Nvidia and AMD.

Jane Street announces a new puzzle challenging participants to reverse engineer an ASIC from its GDS layout, recover a netlist, infer the circuit's purpose, and find the final answer.

SK Hynix introduces CMM-Ax, an ASIC-based CXL-PNM solution developed with Marvell Technology, designed to overcome memory bottlenecks in long-context LLM inference, achieving up to 5.5× higher throughput than GPU-only systems.

This article announces the design and tape-out of what is claimed to be the world's first open source Ethernet switch ASIC, with silicon bring-up expected in mid-November 2025. It discusses the lack of open source networking hardware and the author's motivation to build a switch ASIC as a first step toward an open source router.

Broadcom and Apple have extended their partnership until 2031 to develop custom ASIC chips for AI processing in Apple products, with Apple planning to deploy advanced AI servers by 2027.

An open-source ASIC design that counts down to the heat death of the universe, broadcasting the counter every second over 100Mbps Ethernet.

OpenAI and Broadcom have announced Jalapeño, a custom ASIC designed for large language model inference in data centers. The chip promises substantially better performance per watt than current state-of-the-art.

JPMorgan releases ASIC industry report, predicts AI custom chips entering golden cycle, Broadcom and Marvell are biggest beneficiaries, and expects AI ASIC shipments to surpass GPU for the first time by 2027.

A technical blog post discussing methods for generating device clocks in FPGA and ASIC designs for interfacing with peripherals such as NOR flash and NAND flash.

An experienced chip designer shares insights on the differences between academic and industry chip design, covering goals, risk tolerance, and methodologies, while noting the growing demand for ASIC designers.