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A technical article detailing the author's attempt to understand and program the Gigatron TTL Color Micro-computer, covering its Harvard architecture, CPU instructions, and programming techniques.
This article details a series of low-level optimizations for binary search in Rust, achieving a 6x speedup by leveraging CPU architecture features like branch prediction and SIMD, applied to a scikit-learn gradient boosting use case.
The article analyzes the new ACE specification from the x86 Ecosystem Advisory Group, which extends Intel's AMX for AI matrix multiplication with fixed tile sizes and outer product instructions, comparing it to Arm's SME.
An educational article that explains how ARM64 (AArch64) instructions are encoded in 32-bit fixed-length words, debunking common misconceptions and providing hands-on decoding examples using ADD immediate on Apple Silicon.
A fully functional 8-bit Harvard architecture CPU built from individual logic gates, designed in Logisim-Evolution, with open-source files and documentation. Created by second-year EE students.
A recent benchmark of the famously slow Intel iAPX432 processor reveals that its performance may have been unfairly maligned, as hand-written code outperformed an 8086, suggesting poor compiler optimization was the culprit.
A detailed technical overview of the PC Engine (TurboGrafx-16) CPU, the HuC6280, a fast 8-bit processor based on the 65C02, covering its architecture, clock speeds, and differences from the NES and SNES CPUs.
Raymond Chen explores why x86 compilers universally prefer "xor eax,eax" over "sub eax,eax" to zero a register, attributing it to historical momentum and slightly safer flag behavior rather than technical superiority.
An exploration of unusual circuits found in the Intel 386's standard cell logic, including large multiplexers and non-standard inverters, highlighting the chip's design history and place-and-route techniques.