Tag
A technical blog post explaining the FastLanes Unified Transport Layout, a SIMD-friendly data layout for parallel delta decoding, and how it enables data-parallel processing with wide virtual registers.
This paper presents a nonparametric Bayesian inverse reinforcement learning approach using a Dirichlet process prior to infer multiple latent reward types from expert demonstrations, implementing a collapsed Gibbs sampler with parallelization via Ray for scalability.
A blog post describing a tiny compiler that demonstrates how to lower data-parallel kernels by converting for loops into vectorized loops with lanes and masks, implemented in ~180 lines of Python.