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TicTacBench is a new benchmark for evaluating coding agents' timing closure capabilities in RTL design, revealing that current agents have significant room for improvement and proposing TicTacSkill to enhance performance.
This paper explores using LLM agents for chip design with higher-level abstractions, introducing a workflow called AHRR that combines agent-based HLS design with RTL refinement, achieving a 2.6× speedup over direct RTL design in benchmarks.
This paper introduces a simulation-aware large language model framework for analog IC layout refinement using in-context policy improvement, achieving better post-layout performance with fewer simulations compared to existing methods.
This paper introduces TTARO, an online deep-kernel Bayesian optimization framework that adapts circuit representations at test time using evaluated figure-of-merit labels. It improves sample efficiency for analog circuit topology search, reducing regret AUC by 15.2% over standard BO and 20.7% over fixed deep kernel learning.
GoGoTB is an agentic framework for end-to-end RTL verification that achieves specification-grounded coverage closure, reaching high coverage on 8 designs without human intervention.
This paper presents SINA, an open-source AI pipeline that automatically converts circuit schematic images into netlists with 96.67% accuracy, significantly improving over prior methods by integrating deep learning, OCR, and vision-language models.