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The article explains why false sharing alignment on x64 should be 128 bytes instead of the typical 64 bytes, due to Intel's Sandy Bridge spatial prefetcher that loads cache lines in pairs. It provides reasoning and a benchmark demonstrating the improvement.
This blog post explains cache-conscious data layout in Rust for multi-threaded structures, covering field zoning and the 128-byte rule to avoid false sharing, using an SPSC ring buffer as an example.
Part 1 of a series on low-level system design in Rust covers cache-conscious data layout techniques including field zoning to avoid false sharing, with a focus on multi-threaded structs and the 128-byte rule, using an SPSC ring buffer as an example.