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Cerebras co-founder and CEO Andrew Feldman explains why the company's wafer-scale architecture claims ~2,500× faster memory-to-compute movement than GPUs during LLM decode, since Cerebras keeps model weights in on-chip SRAM rather than HBM.
The article retrospectively reverse-engineers Apple's Neural Engine on the M1 chip, analyzing its architecture and discussing its evolution with the M5 chip's integration into GPU cores.
This article details the process of GPU memory writes, tracing the STG.E instruction through various hardware components like the load/store unit, coalescer, and L1 cache on an RTX 4090.
An educational article explaining the fundamentals of computer memory architecture, including memory hierarchy, CPU cache design, and SSD internals.
The article discusses how rising DDR5 memory prices signal a broader memory bottleneck in AI, particularly the KV cache in softmax attention for LLMs, and highlights post-transformer architectures like linear attention and state space models that aim to reduce memory usage.
Die analysis of the Intel 8087 math coprocessor's fast bit shifter, exploring its architecture and role in floating-point operations.
The article analyzes the AI inference ASIC architectures of Groq, SambaNova, Tenstorrent, and Cerebras, highlighting Cerebras's unique wafer-scale engine design. It discusses the benefits of deterministic latency and high bandwidth for LLM inference, while noting challenges like yield, cost, and KV cache bottlenecks.