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This paper presents the design and end-to-end formal verification of IEEE-754 binary32 and bfloat16 arithmetic for ARCH HDL, a hardware description language intended for AI model generation. The operators are proven correctly rounded using a hybrid approach combining exhaustive SMT equivalence checking and Lean 4 proofs, with synthesizable SystemVerilog output.
The author describes designing a custom CPU at the logic gate level, integrating DDR3 memory with cache, and successfully running Doom on an FPGA, which went viral.
MIT's JARVIS Challenge tested whether AI can accelerate the design, build, and test of a jet engine, finding that AI speeds up engineering but human judgment and manufacturing remain critical.
Alex Mordvintsev introduces MorphoHDL, a minimal language prototype for growing boolean circuits using size-agnostic graph rewrite rules.
A textbook covering the detailed design of RISC-V microprocessors and system-on-chip, including open-source SystemVerilog code and test cases for single-issue, superscalar, and multicore implementations.
A thread analyzing how six AI chip competitors (Tenstorrent, Cerebras, Trainium, TPU, SambaNova, Furiosa) all independently abandoned traditional GPU features like hardware caches and threads, using software-managed SRAM and different programming models, contrasting with NVIDIA's CUDA approach.
The author built a DIY GPU-like parallel computing cluster using 65536 low-cost RISC-V microcontrollers (CH570), achieving QVGA resolution rendering, and solved engineering challenges such as power supply, heat dissipation, and programming automation.
AgRefactor is an LLM-based multi-agent workflow for refactoring software into HLS-compatible programs, featuring a self-evolving memory system and automated refactoring tools, achieving significant speedups on real-world benchmarks.
NVIDIA proposes HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution, achieving 100% benchmark completion across several hardware design suites.
A fully functional 8-bit Harvard architecture CPU built from individual logic gates, designed in Logisim-Evolution, with open-source files and documentation. Created by second-year EE students.
This article reverse-engineers the 69-bit adder at the core of Intel's 8087 floating-point coprocessor from 1980, explaining its architecture and carry-chain techniques.
A technical blog post discussing methods for generating device clocks in FPGA and ASIC designs for interfacing with peripherals such as NOR flash and NAND flash.
This paper presents STG, a structured testbench generation framework for LLM-driven hardware design workflows that reduces token cost and improves verification reliability compared to existing prompt-based approaches.
OpenRTLSet introduces the largest fully open-source dataset for hardware design with over 131,000 Verilog code samples, enabling fine-tuning of LLMs for Verilog code generation.
Alpha-RTL (TTT-RTL) introduces a test-time training framework for RTL hardware optimization, using reinforcement learning with EDA feedback to refine LLM-generated designs. It achieves significant PPA reductions on benchmarks.
StepPRM-RTL is a novel framework combining stepwise trajectory modeling, process-reward modeling (PRM), and retrieval-augmented fine-tuning (RAFT) to improve LLM-based RTL code generation for Verilog and VHDL, outperforming prior methods by over 10% in functional correctness metrics.
Verilog-Evolve is a feedback-driven framework that iteratively refines Verilog code generated by large language models, using functional simulation, synthesis, and timing metrics to promote better candidates and evolve reusable repair skills across tasks.
The article draws parallels between the security flaws in C/C++ and those in Verilog, arguing that the hardware description language's design leads to bugs and that the industry should invest in safer alternatives, similar to the push for memory-safe programming languages in software.
A developer is using AI-assisted CAD (Claude Code) to design a custom wrist-mounted diving computer, compressing what was a multi-week design process into a weekend project. The final device will be 3D-printed and run the Bühlmann ZHL-16C decompression algorithm.
CPPL is a compiler-mediated framework that bridges LLMs and hardware design by using a Python DSL and JSON-based intermediate representation to enable statically checkable, optimizable RTL generation.