hardware-security

Nvidia launches the Open Agent Safety Platform, a toolkit combining open-source software and hardware monitoring to secure AI agents within test environments and prevent unauthorized actions.

NVIDIA launched the Open Agent Safety Platform with OpenShell and Sentry to enforce safety boundaries outside AI agents, preventing them from bypassing controls at the application layer.

The author discusses an unexpected memory value issue encountered while debugging the key management unit in Nordic's nRF54L series, explaining how debugger interactions with internal SoC components can cause such problems.

OpenAI's Noam Brown warns that air-gapping computers may not stop misaligned AI from communicating through indirect methods like CPU temperature changes, highlighting the need to avoid underestimating AI capabilities.

Researchers from Ledger Donjon demonstrated a photon-emission-guided laser fault injection technique to bypass secure debug features on the RP2350 microcontroller, allowing access to secure memory despite permanent debug-disable settings.

GrapheneOS project has announced that Pixel 11 devices no longer support hardware memory tagging (MTE), which may affect security features.

David Chisnall presents CHERI, a hardware capability architecture enabling memory safety and fine-grained compartmentalization through ISA extensions such as ARM Morello, RISC-V, and CHERIoT microcontrollers. The talk emphasizes the importance of practical programming models for secure isolation.

MAGIC is a research paper exploring malicious aging attacks in circuits and cores, focusing on hardware security implications.

The Dabao evaluation board features the Baochip-1x, an open-source, NDA-free SoC with hardware security features and a 700 MHz quad-core RISC-V I/O coprocessor, targeting embedded developers and hobbyists.

This academic paper bridges the gap between experimental characterization and device-level modeling of DRAM read disturbance phenomena (RowHammer and RowPress), presenting TCAD simulations to explain bitflip directions, counts, and minimum aggressor activations, with implications for mitigation techniques.

The paper defines a topology-driven structural manipulability score for gate-level netlists based on path participation, k-core embedding, symmetry, and centrality, and evaluates how well different GNN architectures approximate it across ISCAS85 and EPFL benchmarks, with a case study on Trojan detection.

This paper proposes a lazy arithmetic approach using systolic arrays to close the verification gap for deep neural networks on embedded systems, addressing numerical incompatibilities and hardware vulnerabilities.

A three-person team with AI assistance bypassed Apple's Memory Integrity Enforcement (MIE) in five days using two bugs and a clever idea, demonstrating a significant vulnerability in Apple's hardware-based kernel memory safety stack.

Europe invests over €2 billion in sovereign cloud initiatives to reduce US legal exposure, but these clouds largely rely on Intel and AMD processors whose management engines (ME/PSP) operate below the OS, creating a hidden channel that current certifications do not assess, undermining claims of extraterritorial immunity.

The article discusses the vulnerability of consumer atomic clocks to signal spoofing via audio harmonics, detailing the technical challenges of receiving NIST's WWVB radio signals on the US East Coast due to ionospheric propagation issues.