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Ujval Kapasi of NVIDIA delivers a PyTorchCon 2026 keynote on what agentic workloads demand from the PyTorch stack, using NVIDIA Vera Rubin as a case study for hardware-software co-design across CPUs, GPUs, memory, and networking, covering optimizations in PyTorch, Triton, and vLLM.
This paper proposes FIBER, a novel GPU execution model that decouples thread-register ownership to enable dynamic parallelism and fine-grained scheduling, achieving significant performance improvements in tensor computations for AI workloads like LLMs.
MiCoPro presents an end-to-end hardware/software co-design framework for mixed-precision quantization, using a hardware-aware proxy model to search optimal layer-wise bitwidths under latency constraints and deploy directly to edge hardware, achieving up to 40% latency reduction with less than 3% accuracy drop.
Proposes RED-PIM, an algorithm-architecture co-design that reduces inter-bank data movement from O(N^2) to O(N) and shrinks attention matrices, achieving significant inference time reductions (16% to 99.99%) for transformer models.
This paper proposes a hardware-software co-design framework for N:M sparse vision Transformer inference, achieving over 2.2× latency speedup on GPUs while maintaining accuracy through a novel CUDA kernel (MD-SpMM) and a deployment-aware sparsity search.
NVIDIA launches a series on AI Model Co-Design, starting with how model dimensions affect GPU performance, which the author says covers the 80/20 of inference optimization fundamentals.
This survey comprehensively reviews resource-efficient architectures and hardware-software co-design for green AI, covering efficient model construction, training/deployment strategies, and sustainable hardware, aiming to guide sustainable large model development.
This tweet discusses the convergence of ML research on attention-based, matmul-optimized algorithms due to hardware constraints, drawing on the 'hardware lottery' concept and noting OpenAI's 9-month chip tape-out as a potential sign of hardware-research co-design.
This paper proposes DxPTA, a novel design space exploration methodology for efficient HW/SW co-design of photonic transformer accelerators that meet area, power, energy, and latency constraints. It achieves up to 15.2x faster searching time than exhaustive approaches, enabling efficient PTA designs for diverse transformer models.
This paper proposes a model-native computing architecture, envisioning future system design through the lens of computer architecture.
The author notes that 'thought to text' is a promising field currently being explored by many teams, emphasizing the importance of hardware-software co-design for successful implementation.