hdl

This paper presents the design and end-to-end formal verification of IEEE-754 binary32 and bfloat16 arithmetic for ARCH HDL, a hardware description language intended for AI model generation. The operators are proven correctly rounded using a hybrid approach combining exhaustive SMT equivalence checking and Lean 4 proofs, with synthesizable SystemVerilog output.

The article draws parallels between the security flaws in C/C++ and those in Verilog, arguing that the hardware description language's design leads to bugs and that the industry should invest in safer alternatives, similar to the push for memory-safe programming languages in software.