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The paper proposes improvements to the optimization problem in combination loss analysis using modern techniques and AlphaEvolve, yielding an improved upper bound on the matrix multiplication exponent.
This article provides a step-by-step guide to calculating the Discrete Fourier Transform (DFT) by hand, demonstrating that it involves matrix multiplications similar to those in deep neural networks.
A walkthrough of backpropagation by hand through a 3-layer network using matrix multiplication, showing all 11 steps from gradients to weight updates.
A systematic exploration of FP32 matrix multiplication optimization on AMD Zen 3, achieving 85.30 GFLOPS (63.5% of theoretical peak) using AVX2/FMA intrinsics, surpassing naive implementation by 56.5x and matching optimized libraries.
This article explains how systolic arrays handle over 95% of AI chip compute, detailing their design, modes of operation, and why they are efficient for matrix multiplication.
The article analyzes the new ACE specification from the x86 Ecosystem Advisory Group, which extends Intel's AMX for AI matrix multiplication with fixed tile sizes and outer product instructions, comparing it to Arm's SME.
Google's TPU uses the systolic array architecture from 1978 to accelerate matrix multiplication with less memory movement. The post shares links to the original paper and TPU design, and suggests building a small-scale version on an FPGA.
The x86 Ecosystem Advisory Group has published the AI Compute Extensions (ACE) specification, defining new x86 instructions and register state for accelerating matrix multiplication and reduced precision data formats in machine learning workloads.
The author details the process of optimizing custom matrix multiplication kernels in Swift to train a Large Language Model on Apple Silicon, aiming to outperform C implementations by leveraging CPU, SIMD, AMX, and GPU capabilities.
A technical deep-dive into achieving peak TOPS performance on the AMD Ryzen AI 7 350 NPU, comparing it to Xilinx AIE-ML v2 AI engines and explaining the hardware architecture for matrix multiplication workloads.