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This blog post details the hardware path of a GPU memory read instruction on an NVIDIA RTX 4090, explaining how a CUDA kernel accesses memory through components like L1 cache and DRAM for performance insights.
This technical blog post explains the performance impact of memory alignment in SIMD vectorization, covering architectures with strict alignment requirements, cacheline crossing, and the behavior of modern CPUs.
The article explains Non-Uniform Memory Access (NUMA), its historical context, and how it affects performance in multi-socket servers, while also introducing Edera's work on making Xen-based virtualization NUMA-aware end-to-end.