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This blog post explores how to make RISC-V execution faster on non-RISC-V machines using an ahead-of-time recompiler that connects basic blocks with tail calls and leverages Clang's preserve_none calling convention, as part of the OpenVM project at Axiom.
A detailed comparison of power consumption for the ESP32-C6 microcontroller across three software frameworks: Arduino, Zephyr RTOS, and ESP-IDF, using standardized testing methodologies.
At the RISC-V Summit Europe 2026, Krste Asanović declared the open-standard ISA's state as strong, highlighting its expansion into high-performance server-class silicon and adoption by major tech companies like Qualcomm, Nvidia, and Google.
RISCBoy is an open-source portable gaming console built with a RISC-V CPU and raster graphics pipeline, implemented on an iCE40 FPGA. The project includes the processor design, graphics hardware, PCB layout, and is fully open-source.
A textbook covering the detailed design of RISC-V microprocessors and system-on-chip, including open-source SystemVerilog code and test cases for single-issue, superscalar, and multicore implementations.
The author built a DIY GPU-like parallel computing cluster using 65536 low-cost RISC-V microcontrollers (CH570), achieving QVGA resolution rendering, and solved engineering challenges such as power supply, heat dissipation, and programming automation.
A hardware enthusiast built an immersion-cooled supercluster using 8192 RISC-V microcontrollers (CH570) and shared their challenges and solutions regarding clock, SPI signals, and production capacity.
Tenstorrent announced at TT-Deploy Japan faster AI inference for Kimi K2.6, LTX 2.3, and DeepSeek-R1 on their hardware, plus the licensable TT-Ascalon S RISC-V CPU for agentic AI.
Pine64 launched the PineVoice, a $50 RISC-V smart speaker designed for Home Assistant tinkerers, featuring open-source firmware and local voice control via the Wyoming protocol.
QSOE 0.1, a QNX-inspired operating system with selectable kernels (Skimmer microkernel or seL4), has been released. It targets 64-bit RISC-V hardware and is available under Apache-2.0.
Yuri Zaporozhets of QRV Systems has built a RISC-V-based personal computer and a mainframe on an FPGA, and rewritten QNX twice. His latest OS QSOE is gaining attention in the FOSS world.
QSOE project v0.1 is released, providing a QNX-compatible operating system with two microkernel variants (custom Skimmer kernel and seL4-based), shared userspace, and support for SiFive Unmatched RISC-V hardware.
Review of the MilkV Jupiter 2 single-board computer featuring the SpacemiT K3 RISC-V SoC with 16 cores and vector compute, exploring its capabilities for running AI inference workloads.
Espressif announced the ESP32-S31, a dual-core RISC-V SoC with Wi-Fi 6, Bluetooth 5.4 LE, Ethernet, and advanced security features, targeting IoT and multimedia applications.
A detailed guide on connecting a JLink JTAG probe to the Pinecil soldering iron via its breakout board to enable hardware debugging of the Bouffalo Lab BL706 MCU (SiFive E24 core) using JLinkGDBServer and GDB, particularly useful for Zephyr RTOS development.
The author open-sourced a custom AI accelerator (atik) implemented on FPGA with native BF16 and attention support, demonstrating significant speedups over PyTorch for various models.
ByteDance is developing custom CPUs using Arm and RISC-V architectures to support its AI infrastructure and reduce reliance on Intel and AMD due to long processor delivery times.
Riscrithm is a high-level macro-assembly dialect for RISC-V, written in Go, that compiles readable code into pure RISC-V assembly with optional optimization.
Demonstrates running a DCGAN with 12.6M int8 quantized parameters on a low-cost RISC-V microcontroller (CH32H417), generating 64x64 cat faces in 26 seconds using pure C inference and quantum entropy sampling.
A report on the RISC-V architecture's floating point capabilities and updates.