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The article details the creation of zSST, a SystemVerilog implementation of 3dfx Voodoo Graphics for FPGA, enabling a DOS PC with Voodoo graphics to run classic games like Tomb Raider.
XLS is an experimental high-level synthesis toolchain from Google that generates synthesizable hardware designs from high-level descriptions, aimed at accelerating hardware-software co-design in the end-of-Moore's-law era.
This paper evaluates the robustness of LLM-generated SystemVerilog assertions under semantics-preserving RTL transformations, finding that point accuracy can hide substantial instability and advocating for robustness-aware evaluation in AI-assisted hardware verification.
This post promotes 'The FPGA Programming Handbook', a guide to FPGA design using SystemVerilog and VHDL with practical projects for hands-on learning.
This paper presents the design and end-to-end formal verification of IEEE-754 binary32 and bfloat16 arithmetic for ARCH HDL, a hardware description language intended for AI model generation. The operators are proven correctly rounded using a hybrid approach combining exhaustive SMT equivalence checking and Lean 4 proofs, with synthesizable SystemVerilog output.