Show HN: Write, simulate and synthesize VHDL/Verilog in the browser

# RisingEdge.pro | Learn Hardware Design Interactively Source: [https://risingedge.pro/](https://risingedge.pro/) ## LearnVHDLandSystemVerilog by writing real code\. ``` -- A 4-bit counter: counts up while en is highlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity pulse_counter isport ( clk : in std_logic; rst : in std_logic; en : in std_logic; count : out std_logic_vector(3 downto 0) );end entity pulse_counter;architecture rtl of pulse_counter issignal count_r : unsigned(3 downto 0);begin-- One register and one adder: that's the-- whole design once it reaches siliconprocess (clk) isbeginif rising_edge(clk) thenif rst = '1' then count_r <= (others => '0');elsif en = '1' then count_r <= count_r + 1;end if;end if;end process; count <= std_logic_vector(count_r);end architecture rtl; ``` 1 Write Real VHDL or SystemVerilog in a full editor with instant syntax feedback\. 2 Run GHDL and Icarus simulate your design against a testbench; Yosys synthesizes it\. All in seconds\. 3 See Explore interactive waveforms and a block diagram of what your code became\. Click any block to see the code behind it\. ## Instant Feedback Submit your code, get simulation results and synthesis reports in seconds\. Fix, iterate, learn\. ## Live Waveforms See your simulation results as interactive waveform diagrams, right in the browser\. ## Guided Curriculum Structured lessons from basics to advanced, with challenges to test your understanding at every step\. ## Multi\-Language Write VHDL or SystemVerilog\. Both run on the same real EDA toolchain\. ## Practice Challenges Story\-driven HDL challenges with real testbenches, free for everyone\. Pick one and solve it in your browser\. ## No Setup Required Skip the hours of tool installation and expensive licenses\. Everything runs in your browser, ready in seconds\. ## Start learning\. Start building\. Follow the course, jump into challenges, or bring your own code\. > “If someone goes through this course and does the practice problems, I would imagine they are easily able to pass most coding interviews for hardware design\.” \- Andrew, early user## Come build with us\. RisingEdge is built in the open with hardware engineers\. Sign up free, no invite needed\. Solve challenges, share your runs, and tell us what should come next\.