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This post promotes 'The FPGA Programming Handbook', a guide to FPGA design using SystemVerilog and VHDL with practical projects for hands-on learning.
RisingEdge.pro is a browser-based platform for learning and practicing hardware design by writing, simulating, and synthesizing VHDL and SystemVerilog code using real EDA tools like GHDL, Icarus, and Yosys, with interactive waveforms and guided lessons.
This article describes the CRC Generator, a command-line tool for generating Verilog/VHDL CRC code, and its archival on GitHub by Julia Desmazes to preserve the tool originally by Evgeni Stavinov.