Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

Hugging Face Daily Papers Papers
differentiable-logic-gate-networks eeg-classification edge-devices low-latency brain-computer-interfaces boolean-circuits binarized-neural-networks

Summary

This paper introduces Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative to conventional neural networks for real-time EEG classification on edge devices, achieving competitive performance with significantly lower latency and model size.

Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3times higher latency and 14times larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10times increase in model scale, achieving a peak speedup of 2.9times over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic
Original Article
View Cached Full Text

Cached at: 07/24/26, 05:06 AM

Paper page - Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

Source: https://huggingface.co/papers/2607.18149

Abstract

Real-timeEEGclassificationonedgedevicesisbottleneckedbythefloating-pointarithmeticofconventionalneuralnetworks.WeinvestigatedDifferentiableLogicGateNetworks(Diff-Logic)asahardware-nativealternativethatcompilesmodelsintopureBooleancircuitsexecutableviabitwiseCPUoperations.Throughrigorousiso-parameterexperimentsacrossfourEEGdatasetsspanningtwoclassificationtasks,binarydementiadetectionand3-classemotionrecognition,wecomparedDiff-Logicagainstmatched-capacityMulti-LayerPerceptron(MLP)andBinarizedNeuralNetwork(BNN)baselinesatfourcomplexitytiers(50k-500kparameters).Ondementiascreening,Diff-Logicachieved80.2%MacroF1,outperformingtheMLPbaselineby6.8%.Onemotionrecognition,theMLPretainedamoderateperformanceadvantagebutincurreda2.3timeshigherlatencyand14timeslargermodelsizewhendeployedonapower-constrained(7W)NvidiaJetsonOrinNanoCPU(Single-core).Critically,Diff-Logicinferencetimeremainednearlyconstantacrossa10timesincreaseinmodelscale,achievingapeakspeedupof2.9timesoverMLPsatthelargestcomplexitytier.Ourresultsestablishlogic-basedneuralarchitecturesasapracticalparadigmforresource-constrainedbrain-computerinterfaces,achievingcompetitiveorsuperiorperformancewhilenativelysatisfyingthelatencyandmemoryconstraintsofportableedgedeployment.CodeisavailableonGitHub:https://github.com/Shyamal-Dharia/eeg-difflogic

View arXiv pageView PDFGitHub2Add to collection

Get this paper in your agent:

hf papers read 2607\.18149

Don’t have the latest CLI?curl \-LsSf https://hf\.co/cli/install\.sh \| bash

Models citing this paper0

No model linking this paper

Cite arxiv.org/abs/2607.18149 in a model README.md to link it from this page.

Datasets citing this paper0

No dataset linking this paper

Cite arxiv.org/abs/2607.18149 in a dataset README.md to link it from this page.

Spaces citing this paper0

No Space linking this paper

Cite arxiv.org/abs/2607.18149 in a Space README.md to link it from this page.

Collections including this paper0

No Collection including this paper

Add this paper to acollectionto link it from this page.

Similar Articles

On the Depth Scalability of Logic Gate Networks

arXiv cs.LG

The paper identifies two causes why logic gate networks fail to benefit from increased depth and proposes Input-Anchored Logic Gate Networks (IALGNs) that condition each layer on original inputs, achieving consistent depth-accuracy improvements beyond 100 layers.