Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

# Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement
Source: [https://arxiv.org/html/2608.13767](https://arxiv.org/html/2608.13767)
## Simulation\-Aware In\-Context Policy Improvement for LLM\-Aided Analog Layout RefinementPubID:pubid:979\-8\-3195\-1246\-8\-0/26/$31\.00 ©2026 IEEE

Bingyang Liu, Ziming Wei, Xiaohan Gao, and David Z\. PanAffiliation:Department of Electrical & Computer Engineering, The University of Texas at Austin, TX, USA \{bingyangliu@, zmwei@, xiaohan\.gao@austin\., dpan@ece\.\}utexas\.edu

###### Abstract

Analog IC layout design remains a labor\-intensive iterative process dominated by simulation\-driven refinement\. Although end\-to\-end layout generators accelerate initial placement and routing, they still require experts to manually tune layout optimization parameters with repeated post\-layout simulations for stringent design specifications\. While Bayesian Optimization \(BO\) is widely adopted for parameter tuning in analog IC design, at the layout level it typically requires hundreds to thousands of evaluations, each involving costly parasitic extraction and post\-layout simulation, which makes it impractical\. Recently, Large Language Models \(LLMs\) have demonstrated potential in improving the sample efficiency of such simulation\-driven tuning\. However, their restricted access to geometric layout context and design\-specific heuristics limits their ability to manipulate the layout optimization process\. In this paper, we propose a simulation\-aware LLM multi\-agent framework that performs in\-context policy improvement \(ICPI\) by iteratively updating layout optimization parameters exposed by an analog layout generator through an act–observe–reflect loop on compact structured layout representations\. Experiments on real\-world analog circuits show that, with only tens of post\-layout simulations, our approach improves post\-layout performance over the generator’s built\-in heuristics and BO\-based tuning method\.

## IIntroduction

Analog IC layout design is a highly iterative, simulation\-driven process\. To reach design\-specific performance targets, designers repeatedly modify layouts and run costly post\-layout simulations, and industrial flows still rely on experienced designers to iteratively refine layouts from sparse simulation feedback\. Because this refinement is a matter of reasoning over feedback rather than following a fixed procedure, it has stayed a human\-driven loop, carried out by expert designers\.

In academia, decades of research on analog placement and routing \(P&R\) algorithms and automated layout generators have accelerated initial layout generation, from classical formulations\[[17](https://arxiv.org/html/2608.13767#bib.bib9),[18](https://arxiv.org/html/2608.13767#bib.bib8),[26](https://arxiv.org/html/2608.13767#bib.bib15),[34](https://arxiv.org/html/2608.13767#bib.bib7),[35](https://arxiv.org/html/2608.13767#bib.bib13)\]and domain\-knowledge\-driven methods\[[2](https://arxiv.org/html/2608.13767#bib.bib14),[28](https://arxiv.org/html/2608.13767#bib.bib10),[27](https://arxiv.org/html/2608.13767#bib.bib12),[36](https://arxiv.org/html/2608.13767#bib.bib18),[11](https://arxiv.org/html/2608.13767#bib.bib19)\]to machine\-learning techniques\[[20](https://arxiv.org/html/2608.13767#bib.bib11),[19](https://arxiv.org/html/2608.13767#bib.bib16),[10](https://arxiv.org/html/2608.13767#bib.bib17)\]\. Recent end\-to\-end analog layout generators including ALIGN\[[16](https://arxiv.org/html/2608.13767#bib.bib3),[30](https://arxiv.org/html/2608.13767#bib.bib4)\], MAGICAL\[[37](https://arxiv.org/html/2608.13767#bib.bib6),[5](https://arxiv.org/html/2608.13767#bib.bib1),[4](https://arxiv.org/html/2608.13767#bib.bib5)\], and other frameworks\[[9](https://arxiv.org/html/2608.13767#bib.bib22),[43](https://arxiv.org/html/2608.13767#bib.bib23),[44](https://arxiv.org/html/2608.13767#bib.bib24)\]optimize wirelength\-centric analytical objectives augmented with heuristics and manually specified constraints\. However, the real post\-layout performance is far more complex than what these analytical surrogates capture\. Since traditional automated flows typically apply generalized, static heuristics to all designs, they often fail to capture the flexible trade\-offs required for specific high\-performance targets\. Therefore, designers still need to manually tune layout optimization parameters through repeated simulations, which limits the practical adoption of such tools\.

![Refer to caption](https://arxiv.org/html/2608.13767v1/Fig1.Intro.png)Fig\. 1:Comparison of four simulation\-driven analog layout flows built on end\-to\-end layout generators: manual tuning, simulation\-based Bayesian optimization, LLM\-interactive design via natural language only, and our ICPI flow over layout optimization parameters\.A natural question is whether algorithms can automatically explore better settings of layout optimization parameters in analog layout generators based on simulation feedback\. Simulation\-based tuning with Bayesian Optimization \(BO\) has been widely used for analog sizing tasks\[[39](https://arxiv.org/html/2608.13767#bib.bib25),[3](https://arxiv.org/html/2608.13767#bib.bib26),[24](https://arxiv.org/html/2608.13767#bib.bib27),[7](https://arxiv.org/html/2608.13767#bib.bib28),[8](https://arxiv.org/html/2608.13767#bib.bib21),[15](https://arxiv.org/html/2608.13767#bib.bib43)\]\. However, BO typically requires hundreds to thousands of samples per design, which is impractical for layout, where each sample involves costly parasitic extraction and post\-layout simulation\. The simulation budget is often limited to only tens of runs per design, which falls far short of the sampling requirements for effective exploration through BO\.

Recent work has explored leveraging the reasoning capabilities of Large Language Models \(LLMs\) to improve the sample efficiency of such simulation\-based methods\[[14](https://arxiv.org/html/2608.13767#bib.bib29),[40](https://arxiv.org/html/2608.13767#bib.bib30),[23](https://arxiv.org/html/2608.13767#bib.bib31),[1](https://arxiv.org/html/2608.13767#bib.bib32),[33](https://arxiv.org/html/2608.13767#bib.bib44)\], suggesting that LLMs might help make better use of scarce evaluations\. Compared with front\-end sizing, back\-end layout offers a particularly suitable setting for LLMs: automated layout generators including MAGICAL\[[37](https://arxiv.org/html/2608.13767#bib.bib6),[5](https://arxiv.org/html/2608.13767#bib.bib1),[4](https://arxiv.org/html/2608.13767#bib.bib5)\]expose semantically meaningful layout optimization parameters within their placement and routing algorithms, such as symmetry constraints and routing priorities\. These structured parameters naturally align with the ability of LLMs to reason about circuit structure and layout trade\-offs\. However, two challenges still hinder their use for layout design automation\. First, the LLM must perceive geometric layout changes through a faithful, evolving state representation rather than vague textual descriptions\. Second, it must learn to adjust layout optimization parameters under a tight post\-layout simulation budget\. Prior LLM\-powered efforts for analog layout design\[[22](https://arxiv.org/html/2608.13767#bib.bib20),[32](https://arxiv.org/html/2608.13767#bib.bib2)\]largely rely on natural\-language descriptions of layout as input, which can be inherently ambiguous\. They also inject domain knowledge mainly through prompt engineering and case\-specific examples that often need to be rebuilt in new designs\. A separate line of recent work orchestrates the full intent\-to\-layout flow with LLM agents, where constraint\-driven generation produces the layout and post\-layout metrics are fed back to select the best implementation among complete attempts\[[42](https://arxiv.org/html/2608.13767#bib.bib45)\]\. Because such flows maintain neither an explicit layout state nor accumulated design\-specific experience that guides how feedback should update layout optimization parameters, the two challenges above remain open there as well\. These unresolved challenges make it difficult to substantially and reliably improve analog layout generation in a simulation\-aware and scalable manner\. As summarized in Fig\.[1](https://arxiv.org/html/2608.13767#S1.F1), current simulation\-driven flows therefore rely on manual tuning, simulation\-based BO, or natural\-language\-only LLM interaction on top of such generators, each with its own limitations under tight post\-layout simulation budgets\.

In this paper, we introduce a simulation\-aware multi\-agent framework that performs in\-context policy improvement \(ICPI\) by iteratively updating a set of exposed layout optimization parameters\. Here, layout optimization parameters refer to generator\-exposed placement and routing parameters, including net weights, placement bias, symmetry constraints, routing priorities, and wire widths\. The framework treats layout refinement as an adaptive process that evolves a design\-specific policy for each circuit instance under a fixed budget of tens of post\-layout simulations\. It exposes current geometry, constraints, and metrics through a compact, LLM\-friendly intermediate representation, the layout state, and retains simulation\-verified experience in a design journal for retrieval and reflection across rounds, all without updating model weights\. In each iteration, the agents select one family of layout optimization parameters to adjust, propose concrete edits, observe feasibility and post\-layout feedbacks, and record the resulting reflections as new experience\. Our main contributions are summarized as follows:

- •We design a compact, LLM\-friendly layout state that contains structured, multi\-level information including circuit connectivity, device locations, exposed layout optimization parameters, parasitic summaries, and post\-layout simulation outcomes\. This structured state replaces purely natural\-language layout descriptions and enables state\-aware reasoning during refinement\.
- •We build a simulation\-aware act–observe–reflect ICPI loop around a mature analog layout generator, exposing a structured set of layout optimization parameters for placement and routing refinement\. In each round, the agents update one parameter family based on the current layout state and sparse post\-layout feedback, while storing validated experience in a persistent design journal\.
- •We validate the framework on two OTA benchmarks across different technologies and scales of the parameter space\. Under the small budget of post\-layout simulations, our method achieves better post\-layout performance than the generator’s built\-in heuristics, BO\-based tuning, and a non\-ICPI baseline\.

The rest of the paper is organized as follows\. Section[II](https://arxiv.org/html/2608.13767#S2)describes the background, Section[III](https://arxiv.org/html/2608.13767#S3)explains the detailed algorithm and implementation, Section[IV](https://arxiv.org/html/2608.13767#S4)demonstrates the results, and Section[V](https://arxiv.org/html/2608.13767#S5)concludes the paper\.

## IIPreliminaries

### II\-AIn\-Context Policy Improvement and Self\-Feedback

Recent work on the self\-feedback and internal consistency of LLMs shows that they can improve their behavior at test time by structuring feedback, reflection, and retrieval around their own outputs\. Self\-refinement methods\[[25](https://arxiv.org/html/2608.13767#bib.bib42),[6](https://arxiv.org/html/2608.13767#bib.bib41)\]follow a propose–feedback–refine pattern: the model first produces an answer, then generates natural\-language feedback or confidence signals, and finally rewrites or abstains based on this feedback, yielding quality gains under fixed weights\. Beyond purely in\-context refinement, self\-improvement methods further exploit self\-generated signals for training, including rationales, scores, and language feedback\[[12](https://arxiv.org/html/2608.13767#bib.bib40),[29](https://arxiv.org/html/2608.13767#bib.bib38)\]\. Lianget al\.\[[21](https://arxiv.org/html/2608.13767#bib.bib39)\]further unify these approaches under a common view where behavior is improved by exploiting self\-generated evaluation signals\. Here, we use the term in\-context policy improvement \(ICPI\) to refer specifically to the test\-time variant with frozen weights, where the “policy” is realized by prompts, retrieved memories, and structured context rather than by parameter updates\.

ICPI ideas also appear in multi\-step agents and domain\-specific optimization\. ReAct\-style agents\[[38](https://arxiv.org/html/2608.13767#bib.bib34)\]interleave chain\-of\-thought reasoning with environment actions, and Reflexion\[[31](https://arxiv.org/html/2608.13767#bib.bib35)\]augments this loop with explicit self\-feedback, where the model summarizes failures and proposes strategy updates that are fed into later prompts\. Similar propose–execute–revise patterns underlie code optimization and configuration frameworks\[[13](https://arxiv.org/html/2608.13767#bib.bib36),[41](https://arxiv.org/html/2608.13767#bib.bib37),[45](https://arxiv.org/html/2608.13767#bib.bib33)\], in which the model repeatedly edits programs or settings, runs tests or benchmarks, and uses execution traces to guide further changes\. Across these settings, performance improves because the in\-context state becomes richer over iterations, including past trajectories, feedback, and heuristic rules\.

These studies suggest that ICPI is particularly well suited to tasks where the model’s actions correspond to semantically meaningful controls and the environment returns rich, domain\-specific signals each round\. Analog layout back\-end optimization exhibits both properties: automated generators expose interpretable layout optimization parameters including symmetry constraints, wirelength weights, routing priorities, and wire widths and spacings, while parasitic extraction and post\-layout simulation provide high\-value though costly feedback\. This makes simulation\-aware ICPI well suited to our setting and motivates the structured layout state, design journal, and iterative scheme introduced in this work\.

### II\-BEnd\-to\-end Analog Layout Generator

Modern end\-to\-end analog layout generators build on decades of research on analog placement and routing algorithms to produce layouts directly from circuit netlists, technology information, and user constraints\. Systems such as MAGICAL\[[37](https://arxiv.org/html/2608.13767#bib.bib6),[5](https://arxiv.org/html/2608.13767#bib.bib1),[4](https://arxiv.org/html/2608.13767#bib.bib5)\], ALIGN\[[16](https://arxiv.org/html/2608.13767#bib.bib3),[30](https://arxiv.org/html/2608.13767#bib.bib4)\], and recent analog P&R frameworks\[[9](https://arxiv.org/html/2608.13767#bib.bib22),[43](https://arxiv.org/html/2608.13767#bib.bib23),[44](https://arxiv.org/html/2608.13767#bib.bib24)\]share a broadly similar pipeline: given a schematic and high\-level constraints, they first place devices, then legalize the placement to satisfy design rules while preserving key relations, and finally run an analog\-aware router that enforces symmetry, spacing, and other heuristics\. This integrated place–legalize–route flow systematically encodes many analog layout requirements into analytical objectives, substantially reducing manual effort for producing a DRC\-clean first\-pass layout\.

Despite this progress, most practical flows still rely on designers to provide and tune constraints and tool\-level parameters, including symmetry groups, optimizer configurations, wire spacing options, and a small set of global weights that balance different objectives\. In principle, analog layout generators could expose much finer\-grained net\-level optimization parameters, including initial device positions or anchors, well\-cluster assignments, per\-net wirelength weights, routing width and spacing options, and per\-net routing priorities\. However, the large number of such layout optimization parameters makes systematic manual tuning impractical\. As a result, these settings often remain fixed across simulation iterations and even across designs, which leaves a large portion of the design space underexplored\. In this work, we modify a place\-and\-route kernel derived from the open\-source analog layout generator MAGICAL\[[37](https://arxiv.org/html/2608.13767#bib.bib6),[5](https://arxiv.org/html/2608.13767#bib.bib1),[4](https://arxiv.org/html/2608.13767#bib.bib5)\]to explicitly surface a structured subset of such net\-level layout optimization parameters, serving as the action space for the ICPI framework described next\.

![Refer to caption](https://arxiv.org/html/2608.13767v1/Fig2.Flow.png)Fig\. 2:Overview of the proposed LLM multi\-agent ICPI framework\. Light\-green boxes represent LLM agents executing an act–observe–reflect loop within the yellow region\. Colored arrows denote observation \(green\), action \(red\), and reflection \(blue\) steps\. The right panels illustrate the structured layout state and design journal, where color\-coded labels distinguish simulation feedback \(purple\) from the parameter families \(yellow\) detailed in Table[I](https://arxiv.org/html/2608.13767#S3.T1)\.

## IIIFramework

As discussed in Section[I](https://arxiv.org/html/2608.13767#S1), we focus on two challenges in LLM\-aided simulation\-aware analog layout refinement: \(i\) how to give the LLM precise access to the evolving layout beyond ambiguous natural\-language descriptions, and \(ii\) how to improve decisions over layout optimization parameters across iterations under a budget of only tens of expensive post\-layout simulations\. As shown in Figure[2](https://arxiv.org/html/2608.13767#S2.F2), we address these challenges through three core components: a structured*layout state*that synchronizes the current layout and feedback, a persistent*design journal*that stores design\-specific experience across rounds, and a simulation\-aware act–observe–reflect loop driven by three agents, namely a Supervisor, an Executor, and a Reflector\. In addition, a one\-shot Analyzer provides circuit\-level prior hints to prune the search space before iterative refinement\. Table[I](https://arxiv.org/html/2608.13767#S3.T1)summarizes the exposed parameter families that define the action space of this ICPI loop\.

### III\-AAction Space and Circuit\-Level Analysis

TABLE I:Layout optimization parameter families used in ICPI\.Param\. FamilyEffectNet weightsIncrease the weight of selected nets in the placement objective\.Placement biasBias selected devices toward preferred layout directions in placement\.SymmetryEnforce symmetry constraint on selected devices during placement and legalization\.PriorityPrioritize routing on critical nets\.Wire widthsTrade off parasitic resistance and capacitance during routing\.Our framework runs on top of an analog layout generator derived from the open\-source layout generator MAGICAL\[[37](https://arxiv.org/html/2608.13767#bib.bib6),[5](https://arxiv.org/html/2608.13767#bib.bib1),[4](https://arxiv.org/html/2608.13767#bib.bib5)\], with extended PDK support and additional interfaces that expose layout optimization parameters\. We keep the underlying optimization algorithms unchanged, but explicitly expose a structured set of layout optimization parameters that can be updated by the LLM agents during refinement\. In this work, we uselayout optimization parametersto refer to the generator\-exposed placement and routing parameters that directly influence layout evolution during optimization, rather than generic tool hyperparameters\. As summarized in Table[I](https://arxiv.org/html/2608.13767#S3.T1), these parameters are organized into five interpretable parameter families: net weights, placement bias, symmetry constraints, routing priorities, and wire widths\. These parameters have direct geometric or electrical implications, including pulling devices on critical nets closer in placement, biasing selected devices toward preferred directions, tightening matching on sensitive structures, prioritizing routing resources, and trading off parasitic resistance and capacitance through wire width\. In the following, we treat this parameter space as the action space of the ICPI loop, while the resulting parameter settings and their geometric consequences are encoded back into the layout state for subsequent rounds\.

Although the exposed parameter space is much more structured than raw layout editing, it is still combinatorially large under even coarse discretization, especially when applied across a large number of nets and devices\. Under a budget of only tens of expensive post\-layout evaluations, purely black\-box exploration can cover only a very small fraction of this space\. We therefore introduce an off\-loop Analyzer that processes the netlist once before iterative refinement\. It decomposes the design into stages and functional blocks, identifies critical devices and nets that are sensitive to mismatch or parasitics, and suggests candidate symmetry constraints together with rough importance scores for different devices and nets\. Intuitively, this step uses the LLM’s reasoning ability and pretrained circuit knowledge to separate likely critical structures from background details\. These outputs are reused in every round without re\-parsing the netlist, allowing the Supervisor and Executor to focus on a pruned subset of parameters and likely critical structures\. In this sense, the Analyzer serves as a circuit\-level prior that improves search efficiency, but the main adaptation during refinement still comes from the iterative ICPI loop itself\. In practice, this pruning is especially important because the exposed parameters are heterogeneous: some primarily affect placement geometry, while others mainly affect routing parasitics or matching\-related constraints\. The Analyzer therefore does not attempt to predict the final best setting directly, but instead narrows the search to parameter families and structures that are more likely to matter under sparse post\-layout feedback\.

### III\-BLayout State

As discussed earlier, we consider two key challenges\. The first is how to convey layout information to the LLM without exposing raw polygons or the full GDS description\. Polygon\-level representations are verbose and lack explicit circuit structure, while image\-based representations fail to capture circuit topology, making it difficult to associate rectangles with devices and to infer routing connectivity\. We therefore define a layout state as a structured, synchronized intermediate representation of the current layout, as illustrated in Figure[2](https://arxiv.org/html/2608.13767#S2.F2)\. It organizes multi\-level information that matters for refinement into two views: a device\-level view that captures geometry and placement\-related structure, and a net\-level view that captures routing\-related properties and parasitic summaries, as well as current parameter settings\.

Concretely, the layout state combines four types of information\. First, it records structural context, including connectivity, subcircuit membership, bounding boxes, and coordinate\-based geometric features, so that the LLM can reason about where devices and nets sit geometrically and how they are topologically related\. Second, it records the current exposed parameters from Subsection[III\-A](https://arxiv.org/html/2608.13767#S3.SS1), allowing the agents to see which parameter family is currently active and how the layout is being steered\. Third, after each placement\-and\-routing result, it incorporates parasitic extraction summaries that approximately indicate layout quality\. Finally, when post\-layout simulation is run for the current round, it appends the performance results\. By composing structural information, applied parameters, and observed feedback in a single representation, the layout state allows the LLM to answer three questions within a short context window: what the layout looks like now, how it is currently behaving, and which settings produced that behavior\.

### III\-CDesign Journal

The second challenge is how to let the LLM accumulate design\-specific knowledge during optimization, rather than relying only on static prompts or hand\-crafted exemplars\. Prior LLM\-assisted analog layout efforts\[[22](https://arxiv.org/html/2608.13767#bib.bib20),[32](https://arxiv.org/html/2608.13767#bib.bib2)\]mainly inject expertise through fixed instructions, and do not maintain persistent memory of which edits helped or hurt within a particular design\. In contrast, our goal is to keep the prompts largely design\-agnostic and let the model adapt within each design instance through iterative interaction with layout and simulation feedback\.

To support this, we introduce a design journal that serves as cross\-round memory for the ICPI loop\. Each journal entry for roundkkstores a compressed snapshot of the pre\-round layout state, the selected parameter family and intended goal of the round, the concrete edits and outcomes produced by the Executor, and a short reflection on why the update appears beneficial or harmful\. It also records practical experience for failure handling, such as repeated routing or legalization breakdowns caused by overly aggressive settings\. During subsequent rounds, the journal is retrieved as in\-context experience, allowing the agents to reuse previously validated heuristics, avoid repeating unproductive trials, and adapt their parameter decisions to the current design without updating model parameters\.

### III\-DICPI Loop

The ICPI loop follows an act–observe–reflect pattern driven by three agents, as shown in Figure[2](https://arxiv.org/html/2608.13767#S2.F2)\. At the beginning of roundkk, the Supervisor receives the current layout state, the Analyzer’s circuit\-level hints, and the design journal\. Based on recent parasitic and post\-layout feedback, it decides whether the next step should continue refining a previously promising parameter family or explore a different one\. It then selects exactly one parameter familyckc\_\{k\}from the exposed action space in Subsection[III\-A](https://arxiv.org/html/2608.13767#S3.SS1)and formulates a small set of high\-level goals for that family, such as strengthening matching around a sensitive pair or prioritizing routing for a set of critical nets\. In this way, the Supervisor performs policy\-level decision making while keeping attribution at the parameter\-family level\.

The Executor translates the Supervisor’s goals into concrete parameter updates\. It looks up past attempts of the same parameter family in the design journal, uses those experiences to choose which parameters to modify and by how much, and then invokes the layout generator with the proposed settings\. If the generator fails to produce a legal layout, for example, because symmetry becomes over\-constrained or widths become too aggressive, the Executor enters a small traceback loop that rolls back to safer values using failure logs and related journal entries\. The output of this stage is a new legal layout together with an updated layout state containing refreshed parasitic summaries and, when scheduled, post\-layout simulation results\.

After each round, the Reflector compresses the history into a new journal entry\. It summarizes the pre\-round state, records the selected parameters and resulting outcomes, and adds a brief reflection on why the change appears helpful or harmful\. Over time, this journal becomes a design\-specific memory of what has worked, what has failed, and how different parameter families interact with the current circuit\. This persistent memory is what turns repeated prompting into in\-context policy improvement\.

All agents share the same backbone LLM but use role\-specific prompts, similar in spirit to Self\-Refine\[[25](https://arxiv.org/html/2608.13767#bib.bib42)\]and Reflexion\-style\[[31](https://arxiv.org/html/2608.13767#bib.bib35)\]prompting\. The Analyzer receives a structured netlist serialization, whereas the Supervisor receives the current layout state, the Analyzer’s circuit\-level hints, and the design journal\. Both agents use fixed output schemas, while the Executor is constrained to return only concrete parameter updates and short rationales\. The Reflector is prompted to compress the current round into a reusable journal entry\.

## IVExperimental Results

### IV\-AExperimental Setup

We evaluate the proposed framework on two operational transconductance amplifiers \(OTAs\) from different technology nodes and topologies, which are widely used building blocks in analog design\. OTA1 is a two\-stage Miller\-compensated OTA in a 65 nm CMOS process, and OTA2 is a fully differential OTA with common\-mode feedback in a 40 nm process\. Although the benchmark set is limited to two designs, these cases are not toy examples: each candidate requires a full layout\-generation step followed by parasitic extraction, and selected iterations further require post\-layout simulation\. As a result, the optimization budget is fundamentally different from conventional low\-cost parameter search\. This makes the benchmark suitable for evaluating whether structured state, circuit\-level priors, and design\-specific memory can improve search efficiency beyond one\-shot prompting and black\-box optimization\. In both cases,*Gain*denotes the open\-loop gain, while UGB and PM are extracted from the closed\-loop simulations\. For OTA1, the target specifications areGain≥50\\geq 50dB,UGB≥18\\geq 18MHz,CMRR≥80\\geq 80dB, andPM≥60∘\\geq 60^\{\\circ\}\. For OTA2, the targets areGain≥60\\geq 60dB,UGB≥1\.5\\geq 1\.5MHz,CMRR≥80\\geq 80dB, andPM≥60∘\\geq 60^\{\\circ\}\. For both designs, a smaller area is preferred\.

Our implementation builds on a layout generator derived from the open\-source layout generator MAGICAL\[[37](https://arxiv.org/html/2608.13767#bib.bib6),[5](https://arxiv.org/html/2608.13767#bib.bib1),[4](https://arxiv.org/html/2608.13767#bib.bib5)\], with extended PDK support and additional interfaces that expose layout optimization parameters as described in Subsection[III\-A](https://arxiv.org/html/2608.13767#S3.SS1)\. For each candidate layout, we perform parasitic extraction using Siemens Calibre and post\-layout simulation using Spectre within Cadence Virtuoso\. The Analyzer, Supervisor, Executor, and Reflector agents all use GPT\-5 as the shared backbone LLM, while the framework also supports open\-source backbone LLMs through the same interface\.

We compare our framework with three baselines\.Heuristicuses the generator’s built\-in fixed settings of the layout optimization parameters: all net weights are set to 1, all device bias terms are set to 0, symmetry constraints are manually specified, routing priorities are set to 1 for all nets, and wire widths are set to the minimum width for all non\-power nets and to4×4\\timesthe minimum width for power nets\.BOapplies Bayesian optimization over the same exposed parameter space, treating the post\-layout FoM defined below as the objective\.Oursis the full simulation\-aware workflow described in Section[III](https://arxiv.org/html/2608.13767#S3), with the complete ICPI loop enabled\. All optimization\-based methods start from the same initial layout\-optimization parameters\. BO and Ours use the same 31\-candidate optimization horizon, with different post\-layout simulation schedules as described below\. ForOurs, we run 30 iterations per design\. Each iteration invokes the generator and full\-circuit parasitic extraction, while post\-layout simulation is performed every three iterations, adding up to 31 parasitic extractions and 11 post\-layout simulations per design\. Because BO requires the objective value at every iteration, we run both extraction and post\-layout simulation for all 31 of its iterations\.Ours w/o ICPIuses the same 31\-candidate optimization horizon and post\-layout simulation schedule as Ours, but removes the design journal and cross\-round reflection\. Each update is generated without retrieving experience from previous rounds\.\.

To summarize electrical quality, we define a scalar FoM overm∈\{Gain,UGB,CMRR\}m\\in\\\{\\text\{Gain\},\\text\{UGB\},\\text\{CMRR\}\\\}\. For each metric with targetLmL\_\{m\}and valuevmv\_\{m\}, we compute

sm=\{\(vmLm\)2,vm<Lm,1\+vm−Lmvm,vm≥Lm,s\_\{m\}=\\begin\{cases\}\(\\dfrac\{v\_\{m\}\}\{L\_\{m\}\}\)^\{2\},&v\_\{m\}<L\_\{m\},\\\\\[4\.0pt\] 1\+\\dfrac\{v\_\{m\}\-L\_\{m\}\}\{v\_\{m\}\},&v\_\{m\}\\geq L\_\{m\},\\end\{cases\}\(1\)
αPM=min⁡\(\(vPMLPM\)2,1\)\\alpha\_\{\\mathrm\{PM\}\}=\\min\\\!\\left\(\(\\dfrac\{v\_\{\\mathrm\{PM\}\}\}\{L\_\{\\mathrm\{PM\}\}\}\)^\{2\},\\,1\\right\)\(2\)
whereLPM=60∘L\_\{\\mathrm\{PM\}\}=60^\{\\circ\}\. To emphasize violations of minimum performance specifications, we apply a quadratic penalty when a metric falls below its target, while retaining a bounded reward above the target\. Thussm=1s\_\{m\}=1at the target and increases smoothly when the metric exceeds it, whileαPM\\alpha\_\{\\mathrm\{PM\}\}caps the contribution of phase margin once the design is sufficiently stable\. The final FoM is defined as the geometric mean ofsGains\_\{\\mathrm\{Gain\}\},sUGBs\_\{\\mathrm\{UGB\}\}, andsCMRRs\_\{\\mathrm\{CMRR\}\}, multiplied byαPM\\alpha\_\{\\mathrm\{PM\}\}, so FoM is sensitive to degradation in any of the metrics\.

### IV\-BPost\-layout Performance Comparison

TABLE II:Post\-layout performance comparison on OTA1 and OTA2\.OTA1OTA2MethodGain \(dB\)UGB \(MHz\)CMRR \(dB\)PM \(deg\)FoMArea \(μ​m2\\mu\\text\{m\}^\{2\}\)Gain \(dB\)UGB \(MHz\)CMRR \(dB\)PM \(deg\)FoMArea \(μ​m2\\mu\\text\{m\}^\{2\}\)Heuristic47\.6615\.6778\.169\.20\.8693592\.953\.151\.45455\.7059\.40\.6967080\.0BO62\.1853\.8054\.8969\.30\.9794036\.962\.141\.61062\.8070\.40\.8808857\.3Ours w/o ICPI50\.5917\.2487\.6269\.31\.0033288\.355\.701\.61167\.3672\.60\.8686490\.5Ours51\.3918\.69108\.669\.41\.1044031\.462\.721\.59780\.8672\.31\.0386468\.2

In Table[II](https://arxiv.org/html/2608.13767#S4.T2), for each method we report the layout with the highest FoM found within the allowed simulation budget\. Neither BO nor our ICPI framework directly optimizes area, and the objective is purely the electrical FoM, since the exposed parameter space in our current setup contains no explicit area controls\. We therefore report area separately to distinguish gains obtained by enlarging the layout from gains achieved through more effective use of the exposed parameter space\. Nonetheless, area or other multi\-objective scores can be incorporated through the same feedback interface without modifying the loop\.

Furthermore, we observed a qualitative robustness difference\.BOcan produce candidates that are geometrically legal and LVS\-clean yet electrically non\-functional once evaluated\. On several unfavorable parameter combinations, excessive parasitics prevented the loop gain from reaching unity, and these committed candidates were assigned a zero FoM\. In contrast, the infeasibilities encountered byOursarise as backend\-infeasible intermediate proposals, such as over\-constrained symmetry or overly aggressive wire widths that break legalization or routing\. Such proposals are detected from failure logs and rolled back to a nearby feasible setting via the Executor and the design journal before commitment, so all committed layouts fromOursandOurs w/o ICPIare feasible, electrically functional, and LVS\-clean\. This contrast highlights the limitation of black\-box methods that lack physical awareness under sparse simulation feedback\.

For OTA1, the parameter space is relatively modest, so BO can explore it reasonably well and reaches a FoM of0\.9790\.979, slightly lower thanOurs w/o ICPIwith1\.0031\.003\. Even in this smaller search space, however, Ours achieves the highest FoM1\.1041\.104with an area essentially identical to BO, showing that the act–observe–reflect ICPI loop can extract additional performance beyond both one\-shot LLM guidance and black\-box search\. Although the ICPI layout is larger than theHeuristicdesign, this is consistent with our setup, where area is reported separately rather than directly penalized in the objective\. Notably,Ours w/o ICPIalready improves both performance and area over theHeuristic, indicating that our framework can exploit the action space to enhance electrical behavior without necessarily increasing area\.

For OTA2, the action space is much larger, with a parameter dimension roughly two orders of magnitude higher than that of OTA1\. Under the same 31\-candidate optimization horizon, BO improves over the Heuristic on all four electrical metrics, but its CMRR remains below the target and its area increases by more than 25%\. Ours w/o ICPI improves both FoM and area over the Heuristic, although it does not meet the Gain and CMRR targets\. In contrast, Ours meets all four electrical targets and achieves the highest FoM of1\.0381\.038while reducing area relative to both the Heuristic and BO layouts\. Compared with Ours w/o ICPI, the full ICPI loop increases the FoM from0\.8680\.868to1\.0381\.038and slightly reduces area, while keeping UGB above its target\.

![Refer to caption](https://arxiv.org/html/2608.13767v1/Fig5.Layout.png)Fig\. 3:Layout comparison of \(a\) Heuristic and \(b\) Ours on OTA2\.
### IV\-CRuntime and overhead

To isolate the cost of the agent orchestration itself, we profile the agent loop with the same backbone LLM\. Per round, orchestration takes about 37 s and 12k tokens for OTA1 and about 43 s and 17k tokens for OTA2, with input context accounting for over 90% of the tokens, which amounts to roughly 18 to 21 minutes over 30 rounds\. By comparison, parasitic extraction and the post\-layout simulations alone require more than 141 min per design under a conservative lower\-bound timing, before accounting for place\-and\-route\. The LLM orchestration therefore accounts for less than 16% of total wall\-clock time under this bound, and substantially less under realistic timing\. The dominant cost remains the simulation\-driven evaluation that the framework is designed to economize, rather than the agent loop\.

## VConclusion

In this paper, we presented a simulation\-aware LLM multi\-agent framework that wraps a mature analog layout generator and performs in\-context policy improvement over layout optimization parameters through an act\-\-observe\-\-reflect loop driven by sparse post\-layout feedback\. Experiments on real\-world analog circuits show that, with only tens of post\-layout simulations, our approach improves post\-layout performance over the generator’s built\-in heuristics, BO\-based tuning, and a non\-ICPI baseline\. While the framework is effective on the studied designs, scaling it to more complex systems remains challenging due to the growing complexity of state representation and the high cost of simulation\-driven search\. Future work will address these limitations by exploring hierarchical partitioning and more scalable refinement strategies for larger circuits, and by extending the real\-flow evaluation beyond the OTA benchmarks to a broader range of analog blocks\. To support reproducibility, we release a PDK\-free demonstrator111[https://github\.com/bingyang1132/ICLAD2026\-demo\-sim\-aware\-in\-context](https://github.com/bingyang1132/ICLAD2026-demo-sim-aware-in-context)that reproduces the core mechanisms of our framework in a synthetic analog\-layout environment with a swappable LLM backbone\. Overall, this work establishes a viable state\-aware refinement loop for simulation\-driven analog layout optimization that can assist expert designers under tight evaluation budgets\.

## VIAcknowledgment

This work was supported in part by NSF under grant CCF\-2112665, SRC under task 3160\.007, Samsung, UT Austin’s iMAGiNE consortium, and an equipment donation from NVIDIA\.

## References

- \[1\]\(2025\)AnaFlow: Agentic LLM\-based Workflow for Reasoning\-Driven Explainable and Sample\-Efficient Analog Circuit Sizing\.arXiv preprint arXiv:2511\.03697\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1)\.
- \[2\]B\. Basaranet al\.\(1993\)Latchup\-aware placement and parasitic\-bounded routing of custom analog cells\.InProc\. ICCAD,pp\. 415–421\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[3\]A\. F\. Budaket al\.\(2021\)An efficient analog circuit sizing method based on machine learning assisted global optimization\.IEEE TCAD41\(5\),pp\. 1209–1221\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p3.1)\.
- \[4\]H\. Chenet al\.\(2021\)MAGICAL 1\.0: An Open\-Source Fully\-Automated AMS Layout Synthesis Framework Verified With a 40\-nm 1GS/sΣ​Δ\\Sigma\\DeltaADC\.InProc\. CICC,Austin, TX, USA,pp\. 1–2\(en\)\.External Links:ISBN 978\-1\-72817\-581\-2,[Link](https://ieeexplore.ieee.org/document/9431521/),[Document](https://dx.doi.org/10.1109/CICC51472.2021.9431521)Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§I](https://arxiv.org/html/2608.13767#S1.p4.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p2.1),[§III\-A](https://arxiv.org/html/2608.13767#S3.SS1.p1.1),[§IV\-A](https://arxiv.org/html/2608.13767#S4.SS1.p2.1)\.
- \[5\]H\. Chenet al\.\(2021\)MAGICAL: An Open\- Source Fully Automated Analog IC Layout System from Netlist to GDSII\.IEEE MDAT38\(2\),pp\. 19–26\.External Links:ISSN 2168\-2356, 2168\-2364Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§I](https://arxiv.org/html/2608.13767#S1.p4.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p2.1),[§III\-A](https://arxiv.org/html/2608.13767#S3.SS1.p1.1),[§IV\-A](https://arxiv.org/html/2608.13767#S4.SS1.p2.1)\.
- \[6\]X\. Chenet al\.\(2023\)Teaching large language models to self\-debug\.arXiv preprint arXiv:2304\.05128\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p1.1)\.
- \[7\]S\. Duet al\.\(2022\)A surrogate\-based parallel optimization of analog circuits using multi\-acquisition functions\.AEU\-International Journal of Electronics and Communications146,pp\. 154105\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p3.1)\.
- \[8\]D\. Erikssonet al\.\(2019\)Scalable global optimization via local bayesian optimization\.Proc\. NIPS32\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p3.1)\.
- \[9\]X\. Gaoet al\.\(2024\)Joint placement optimization for hierarchical analog/mixed\-signal circuits\.InProc\. ICCAD,pp\. 1–9\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1)\.
- \[10\]A\. Gusmãoet al\.\(2020\)Semi\-supervised artificial neural networks towards analog IC placement recommender\.InProc\. ISCAS,pp\. 1–5\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[11\]K\. Hoet al\.\(2013\)Coupling\-aware length\-ratio\-matching routing for capacitor arrays in analog integrated circuits\.InProc\. DAC,pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[12\]J\. Huang, S\. Gu, L\. Hou, Y\. Wu, X\. Wang, H\. Yu, and J\. Han\(2023\)Large language models can self\-improve\.InProc\. EMNLP,pp\. 1051–1068\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p1.1)\.
- \[13\]S\. Jianget al\.\(2023\)Selfevolve: A code evolution framework via large language models\.arXiv preprint arXiv:2306\.02907\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p2.1)\.
- \[14\]D\. V\. Kocharet al\.\(2025\)Ledro: LLM\-enhanced design space reduction and optimization for analog circuits\.InProc\. ICLAD,pp\. 141–148\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1)\.
- \[15\]Z\. Konget al\.\(2024\)PVTSizing: A TuRBO\-RL\-Based Batch\-Sampling Optimization Framework for PVT\-Robust Analog Circuit Synthesis\.InProc\. DAC,pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p3.1)\.
- \[16\]K\. Kunalet al\.\(2019\)ALIGN: Open\-Source Analog Layout Automation from the Ground Up\.InProc\. DAC,Las Vegas NV USA,pp\. 1–4\(en\)\.External Links:ISBN 978\-1\-4503\-6725\-7,[Link](https://dl.acm.org/doi/10.1145/3316781.3323471),[Document](https://dx.doi.org/10.1145/3316781.3323471)Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1)\.
- \[17\]K\. Lampaertet al\.\(1995\)A performance\-driven placement tool for analog integrated circuits\.IEEE Journal Solid\-State Circuits30\(7\),pp\. 773–780\.External Links:[Document](https://dx.doi.org/10.1109/4.391116)Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[18\]K\. Lampaertet al\.\(1996\)Analog routing for manufacturability\.InProc\. CICC,Vol\.,pp\. 175–178\.External Links:[Document](https://dx.doi.org/10.1109/CICC.1996.510537)Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[19\]Y\. Liet al\.\(2020\)A customized graph neural network model for guiding analog IC placement\.InProc\. ICCAD,pp\. 1–9\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[20\]Y\. Liet al\.\(2020\)Exploring a machine learning approach to performance driven analog IC placement\.InProc\. ISVLSI,pp\. 24–29\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[21\]X\. Lianget al\.\(2024\)Internal consistency and self\-feedback in large language models: A survey\.arXiv preprint arXiv:2407\.14507\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p1.1)\.
- \[22\]B\. Liuet al\.\(2024\)LayoutCopilot: An LLM\-powered Multi\-agent Collaborative Framework for Interactive Analog Layout Design\.arXiv preprint arXiv:2406\.18873\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1),[§III\-C](https://arxiv.org/html/2608.13767#S3.SS3.p1.1)\.
- \[23\]C\. Liuet al\.\(2025\)LLM\-based AI Agent for Sizing of Analog and Mixed Signal Circuit\.arXiv preprint arXiv:2504\.11497\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1)\.
- \[24\]M\. Liuet al\.\(2021\)Parasitic\-aware analog circuit sizing with graph neural networks and Bayesian optimization\.InProc\. DATE,pp\. 1372–1377\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p3.1)\.
- \[25\]A\. Madaanet al\.\(2023\)Self\-refine: Iterative refinement with self\-feedback\.Proc\. NIPS36,pp\. 46534–46594\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p1.1),[§III\-D](https://arxiv.org/html/2608.13767#S3.SS4.p4.1)\.
- \[26\]E\. Malavasiet al\.\(1990\)A Routing Methodology for Analog Integrated Circuits\.\.InProc\. ICCAD,pp\. 202–205\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[27\]R\. Martinset al\.\(2016\)Current\-flow and current\-density\-aware multi\-objective optimization of analog IC placement\.Integration, the VLSI Journal55,pp\. 295–306\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[28\]H\. Ouet al\.\(2013\)Simultaneous analog placement and routing with current flow and current density considerations\.InProc\. DAC,pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[29\]A\. Patelet al\.\(2024\)Large language models can self\-improve at web agent tasks\.arXiv preprint arXiv:2405\.20309\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p1.1)\.
- \[30\]S\. S\. Sapatnekaret al\.\(2023\)The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues\.InProc\. ISPD,Virtual Event USA,pp\. 101–102\(en\)\.External Links:ISBN 978\-1\-4503\-9978\-4,[Link](https://dl.acm.org/doi/10.1145/3569052.3578916),[Document](https://dx.doi.org/10.1145/3569052.3578916)Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1)\.
- \[31\]N\. Shinnet al\.\(2023\)Reflexion: Language agents with verbal reinforcement learning\.Proc\. NIPS36,pp\. 8634–8652\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p2.1),[§III\-D](https://arxiv.org/html/2608.13767#S3.SS4.p4.1)\.
- \[32\]Z\. Wanget al\.\(2024\)ChatPattern: Layout pattern customization via natural language\.InProc\. DAC,pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1),[§III\-C](https://arxiv.org/html/2608.13767#S3.SS3.p1.1)\.
- \[33\]Z\. Weiet al\.\(2025\)TopoSizing: An LLM\-aided Framework of Topology\-based Understanding and Sizing for AMS Circuits\.arXiv preprint arXiv:2509\.14169\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1)\.
- \[34\]L\. Xiaoet al\.\(2010\)Practical placement and routing techniques for analog circuit designs\.InProc\. ICCAD,pp\. 675–679\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[35\]B\. Xuet al\.\(2017\)Hierarchical and analytical placement techniques for high\-performance analog circuits\.InProc\. ISPD,pp\. 55–62\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[36\]B\. Xuet al\.\(2019\)Device layer\-aware analytical placement for analog circuits\.InProc\. ISPD,pp\. 19–26\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1)\.
- \[37\]B\. Xuet al\.\(2019\)MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper\.InProc\. ICCAD,Westminster, CO, USA,pp\. 1–8\(en\)\.External Links:ISBN 978\-1\-72812\-350\-9,[Link](https://ieeexplore.ieee.org/document/8942060/),[Document](https://dx.doi.org/10.1109/ICCAD45719.2019.8942060)Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§I](https://arxiv.org/html/2608.13767#S1.p4.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p2.1),[§III\-A](https://arxiv.org/html/2608.13767#S3.SS1.p1.1),[§IV\-A](https://arxiv.org/html/2608.13767#S4.SS1.p2.1)\.
- \[38\]S\. Yaoet al\.\(2022\)ReAct: Synergizing reasoning and acting in language models\.arXiv preprint arXiv:2210\.03629\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p2.1)\.
- \[39\]S\. Yinet al\.\(2022\)Fast surrogate\-assisted constrained multiobjective optimization for analog circuit sizing via self\-adaptive incremental learning\.IEEE TCAD42\(7\),pp\. 2080–2093\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p3.1)\.
- \[40\]Y\. Yinet al\.\(2024\)ADO\-LLM: Analog design Bayesian optimization with in\-context learning of large language models\.InProc\. ICCAD,pp\. 1–9\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1)\.
- \[41\]C\. Yuet al\.\(2025\)Autonomous code evolution meets NP\-completeness\.arXiv preprint arXiv:2509\.07367\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p2.1)\.
- \[42\]H\. Zhang, W\. Fan, X\. Gao, B\. Liu, R\. Wang, and Y\. Lin\(2026\)PANDA: an LLM\-enhanced performance\-driven analog design framework bridging design intent and layout generation\.InProc\. DAC,Long Beach, CA, USA\.Note:Invited PaperCited by:[§I](https://arxiv.org/html/2608.13767#S1.p4.1)\.
- \[43\]H\. Zhanget al\.\(2023\)SAGERoute: Synergistic analog routing considering geometric and electrical constraints with manual design compatibility\.InProc\. DATE,pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1)\.
- \[44\]H\. Zhanget al\.\(2024\)SAGERoute 2\.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios\.InProc\. DATE,pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.13767#S1.p2.1),[§II\-B](https://arxiv.org/html/2608.13767#S2.SS2.p1.1)\.
- \[45\]Z\. Zhouet al\.\(2024\)ISR\-LLM: Iterative self\-refined large language model for long\-horizon sequential task planning\.InProc\. ICRA,pp\. 2081–2088\.Cited by:[§II\-A](https://arxiv.org/html/2608.13767#S2.SS1.p2.1)\.