VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space

# VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space
Source: [https://arxiv.org/html/2608.02878](https://arxiv.org/html/2608.02878)
###### Abstract

Large language models have shown promise for automated Verilog RTL generation, yet state\-of\-the\-art multi\-agent systems plateau at 95% accuracy on standard benchmarks\. We trace this ceiling to an incomplete*debugging action space*: existing systems restrict which signals the agent can inspect, which time windows it can query, or both, reducing debugging to pattern matching on a narrow, predetermined view of circuit behavior rather than hypothesis\-driven root\-cause analysis\. We present VeriTrace, a multi\-agent system whose Inspector agent operates over a*complete*debugging action space, with independent control over signal selection, time\-window bounds, and iteration depth\. This capability, which we termAgentic Temporal Exploration, enables the agent to form hypotheses about failure causes, query the waveform for evidence, and refine its understanding iteratively, mirroring the exploratory process of human verification engineers\. VeriTrace achieves100% Pass@1on VerilogEval\-V2, the first system to attain perfect functional correctness on this benchmark\. On a shared Claude Sonnet 4\.0 backbone, VeriTrace outperforms the strongest reproduced baseline by \+5\.1%, demonstrating that debugging agency closes the final accuracy gap\.

††publicationid:pubid:979\-8\-3195\-1246\-8\-0/26/$31\.00 ©2026 IEEE## IIntroduction

Modern digital hardware design remains a labor\-intensive process that requires significant expertise in hardware description languages \(HDLs\) such as Verilog or SystemVerilog\[[5](https://arxiv.org/html/2608.02878#bib.bib7),[9](https://arxiv.org/html/2608.02878#bib.bib8)\]\. As chip complexity grows and design cycles shorten, the demand for automated RTL code generation has become increasingly urgent\[[13](https://arxiv.org/html/2608.02878#bib.bib2),[18](https://arxiv.org/html/2608.02878#bib.bib9),[16](https://arxiv.org/html/2608.02878#bib.bib13)\]\. Manual translation from natural language specifications to functionally correct Verilog is error\-prone and time\-consuming, motivating the need for intelligent automation\.

Large language models \(LLMs\) have emerged as promising tools for hardware design automation\[[18](https://arxiv.org/html/2608.02878#bib.bib9),[25](https://arxiv.org/html/2608.02878#bib.bib11)\]\. Recent work has demonstrated that LLMs can generate syntactically valid Verilog code from natural language descriptions, with models like GPT\-4 and Claude achieving non\-trivial pass rates on benchmarks such as VerilogEval\[[13](https://arxiv.org/html/2608.02878#bib.bib2),[19](https://arxiv.org/html/2608.02878#bib.bib3)\]\. These results suggest that LLMs possess sufficient understanding of HDL syntax and basic digital design patterns to serve as the foundation for automated RTL generation\[[19](https://arxiv.org/html/2608.02878#bib.bib3),[36](https://arxiv.org/html/2608.02878#bib.bib16),[26](https://arxiv.org/html/2608.02878#bib.bib12)\]\.

However, single\-agent LLM approaches face fundamental limitations in debugging\. When generated code fails simulation, these systems receive only pass/fail feedback or generic error messages, lacking the detailed signal\-level information needed to diagnose functional bugs\. Multi\-agent systems have begun to address this gap by incorporating waveform\-based debugging feedback\[[10](https://arxiv.org/html/2608.02878#bib.bib1),[37](https://arxiv.org/html/2608.02878#bib.bib4)\], but the feedback alone is not sufficient\. What matters is the*action space*available to the debugging agent: which signals it can select, which time windows it can query, and whether it can issue queries iteratively as its understanding evolves\[[33](https://arxiv.org/html/2608.02878#bib.bib23),[4](https://arxiv.org/html/2608.02878#bib.bib29)\]\.

Table[I](https://arxiv.org/html/2608.02878#S1.T1)summarizes the debugging action spaces of existing multi\-agent systems\. MAGE\[[37](https://arxiv.org/html/2608.02878#bib.bib4)\]introduces state checkpoint printing that captures I/O values at the first error timestamp, but restricts the agent to input and output signals at a single point in time, no signal selection, no temporal freedom, and no iteration\. VerilogCoder\[[10](https://arxiv.org/html/2608.02878#bib.bib1)\]uses AST analysis to automate signal selection and supports iterative tracing, but anchors its waveform display to the first mismatch timestamp\. Although both systems demonstrate that waveform feedback improves functional correctness, neither grants the agent joint control over*which*signals to inspect*and when*\.

TABLE I:Comparison of multi\-agent systems\.We present VeriTrace, a multi\-agent system that closes this action space gap by introducingAgentic Temporal Exploration, a debugging methodology that grants the LLM agent full control over signal selection and time\-window inspection\. Unlike prior approaches, VeriTrace enables iterative waveform queries: the agent selects signals and a time range, observes the result, refines its hypothesis, and queries again until the root cause is identified\. Our contributions are as follows:

![Refer to caption](https://arxiv.org/html/2608.02878v1/fig/Overview.png)Figure 1:Overview of VeriTrace- •We identify*debugging action space completeness*as the key bottleneck in multi\-agent RTL generation and introduce Agentic Temporal Exploration, enabling self\-directed access to arbitrary signals and time windows for hypothesis\-driven code refinement\.
- •We propose VeriTrace, a multi\-agent system built around Agentic Temporal Exploration with a dedicated Inspector Agent for waveform analysis\.
- •Rather than ingesting full VCD waveform dumps, the Inspector queries only the signals and time windows relevant to its current hypothesis, reducing token consumption by 18% and enabling a scalable path toward larger designs\.
- •VeriTrace achieves100% Pass@1 on VerilogEval\-V2, to the best of our knowledge the first open source system to attain perfect functional correctness on this benchmark\.

## IIBackground

### II\-ALLMs for RTL Code Generation

The application of large language models to Verilog generation has progressed along two paths: domain\-specialized models trained on curated RTL datasets\[[15](https://arxiv.org/html/2608.02878#bib.bib15),[36](https://arxiv.org/html/2608.02878#bib.bib16),[7](https://arxiv.org/html/2608.02878#bib.bib17),[3](https://arxiv.org/html/2608.02878#bib.bib28),[12](https://arxiv.org/html/2608.02878#bib.bib31),[6](https://arxiv.org/html/2608.02878#bib.bib32),[14](https://arxiv.org/html/2608.02878#bib.bib33)\], and general\-purpose LLMs such as GPT\-4 and Claude applied directly to hardware description\[[13](https://arxiv.org/html/2608.02878#bib.bib2),[19](https://arxiv.org/html/2608.02878#bib.bib3)\]\. Both paths demonstrate that LLMs have acquired sufficient understanding of HDL syntax and basic digital design patterns\[[25](https://arxiv.org/html/2608.02878#bib.bib11),[19](https://arxiv.org/html/2608.02878#bib.bib3)\], but single\-pass generation alone, without simulation feedback, remains insufficient for reliable functional correctness\[[32](https://arxiv.org/html/2608.02878#bib.bib34)\]\.

### II\-BMulti\-Agent Systems for RTL Generation

To incorporate simulation feedback, recent work has adopted multi\-agent architectures that decompose RTL design into specialized subtasks\. VerilogCoder\[[10](https://arxiv.org/html/2608.02878#bib.bib1)\]introduces a Task and Circuit Relation Graph for plan decomposition and an AST\-based waveform tracing tool that back\-traces signals from mismatched outputs, providing signal\-level context at the point of failure\. MAGE\[[37](https://arxiv.org/html/2608.02878#bib.bib4)\]employs four agent types with a high\-temperature candidate sampling strategy and a state checkpoint mechanism that captures I/O values at the earliest mismatch\. ACE\-RTL\[[8](https://arxiv.org/html/2608.02878#bib.bib18)\]combines a domain\-specialized RTL model with a frontier reasoning LLM through an agentic context evolution loop, where a Reflector analyzes simulation logs and a Coordinator maintains structured debugging history across iterations\. These systems collectively demonstrate that multi\-agent collaboration with simulation\-in\-the\-loop substantially improves functional correctness over single\-pass approaches\[[33](https://arxiv.org/html/2608.02878#bib.bib23),[11](https://arxiv.org/html/2608.02878#bib.bib24),[31](https://arxiv.org/html/2608.02878#bib.bib35)\]\.

### II\-CAgentic Reasoning and Tool Use

The ReAct paradigm\[[35](https://arxiv.org/html/2608.02878#bib.bib5)\]formalizes agentic tool use as an interleaved loop ofThought,Action, andObservation: the agent reasons about its current state, invokes a tool, observes the result, and repeats\. A key finding from the software engineering domain is that the*interface*between agent and tools matters as much as the underlying LLM\[[21](https://arxiv.org/html/2608.02878#bib.bib21)\]\.

SWE\-Agent\[[34](https://arxiv.org/html/2608.02878#bib.bib19)\]showed that action\-space design matters more than model scaling for software agents\. Hardware debugging poses an additional challenge: bugs are spatiotemporal, requiring joint control over signal selection and temporal navigation\[[22](https://arxiv.org/html/2608.02878#bib.bib22),[30](https://arxiv.org/html/2608.02878#bib.bib25),[4](https://arxiv.org/html/2608.02878#bib.bib29),[17](https://arxiv.org/html/2608.02878#bib.bib37),[29](https://arxiv.org/html/2608.02878#bib.bib26),[28](https://arxiv.org/html/2608.02878#bib.bib27),[27](https://arxiv.org/html/2608.02878#bib.bib36)\]\.

![Refer to caption](https://arxiv.org/html/2608.02878v1/fig/Inspector_gram.png)Figure 2:An example of Inspector Agentic Temporal Exploration for Problem 155\.

## IIIMethod

VeriTrace’s multi\-agent architecture follows a deterministic control flow modeled after how human engineers approach RTL design: write code, simulate, inspect failing signals, diagnose the root cause, and repair\. Rather than relying on learned orchestration or dynamic agent allocation, VeriTrace decomposes the task into the same sequential stages a verification engineer would follow, with each stage handled by a specialized agent\.

As shown in Figure[1](https://arxiv.org/html/2608.02878#S1.F1), the system takes a natural language specification and golden testbench if available as input, generates testbench and RTL\. Then, if simulation reports a functional error, enters a closed\-loop cycle of inspection and debugging until all test cases pass\. The key innovation lies in the Inspector agent, which operates over a complete debugging action space to provide hypothesis\-driven diagnostic feedback\.

### III\-ATestbench and RTL Agent

The Testbench Agent modifies the golden testbench to dump all waveforms, enabling the Inspector to query arbitrary internal signals, just as human designers do with commercial tools\[[24](https://arxiv.org/html/2608.02878#bib.bib14)\]\. The RTL Agent generates modules from the specification and modified testbench, with a strict syntax check enforced before simulation\. We follow MAGE\[[37](https://arxiv.org/html/2608.02878#bib.bib4)\]to incorporate the Simulation Judge and High\-Temperature RTL Sampling for the initial pass, avoiding the token\-heavy debugging loop for medium to easy tasks\.

### III\-BInspector: Agentic Temporal Exploration

Complex RTL problems, particularly FSMs with feedback, are rarely solved in a single generation pass\. As established in Section[II\-C](https://arxiv.org/html/2608.02878#S2.SS3), RTL bugs are spatiotemporal: a mismatch observed at timettmay originate many clock cycles earlier in an unrelated logic block\. The Inspector addresses this by separatingdiagnosisfromrepair\. While the Debugger translates diagnostic findings into code edits, the Inspector operates over the complete debugging action space, selecting which signals to examine, which time windows to query, and how many rounds of exploration to perform\.

This separation of diagnosis from repair[1](https://arxiv.org/html/2608.02878#S1.F1)gives each agent a focused context window, avoiding the need for a single agent to handle waveform analysis and code modification simultaneously\.

Figure 2 illustrates how the Inspector, starting from the initial error timestamp, identifies the incorrect state transition through iterative waveform analysis\.

#### III\-B1Observation from Human RTL Verification

When an RTL simulation reports a mismatch, human designers do not examine the failing timestamp in isolation\. In commercial tools such as Synopsys Verdi\[[24](https://arxiv.org/html/2608.02878#bib.bib14),[23](https://arxiv.org/html/2608.02878#bib.bib6)\], the designer selects a suspect signal, inspects its transitions over a chosen time window, forms a hypothesis about which logic block introduced the error, and traces further into that block’s inputs to confirm or revise the hypothesis\. Crucially, it is the designer who decides which signals to examine and when\. Diagnosing such faults requires navigating internal signals, state registers, counters, next\-state logic, across arbitrary time ranges, iteratively, as understanding evolves\.

These observations motivate the Inspector’s design\. An agent restricted to fixed signals or a single timestamp cannot escape the narrow view that makes automated debugging brittle\. The Inspector grants full control over signal selection and time windows, enabling the iterative, hypothesis\-driven process formalized below\.

#### III\-B2Inspector Action Formulation\.

Let𝒮\\mathcal\{S\}denote the natural language specification,CCthe current RTL code,terrt\_\{\\text\{err\}\}the first error timestamp reported by simulation, and𝒲\\mathcal\{W\}the complete waveform generated by the modified testbench\.

At each iterationii, the Inspector selects a set of signals𝝈i\\boldsymbol\{\\sigma\}\_\{i\}and a time window\[tistart,tiend\]\[t^\{\\text\{start\}\}\_\{i\},\\,t^\{\\text\{end\}\}\_\{i\}\]to query\. The agentic waveform tracing tool returns a natural\-language\-style waveform snapshot:

ωi=Trace​\(𝒲,𝝈i,tistart,tiend\)\\omega\_\{i\}=\\textsc\{Trace\}\(\\mathcal\{W\},\\,\\boldsymbol\{\\sigma\}\_\{i\},\\,t^\{\\text\{start\}\}\_\{i\},\\,t^\{\\text\{end\}\}\_\{i\}\)\(1\)
The Inspector follows a ReAct\-style reasoning pattern\[[35](https://arxiv.org/html/2608.02878#bib.bib5)\], interleaving thought and action\. At each step, the Inspector produces a thoughtτi\\tau\_\{i\}that reasons over the accumulated context and decides whether to issue another query or to terminate:

τi,ai=Think​\(𝒮,C,terr,ω1,…,ωi\)\\tau\_\{i\},\\,a\_\{i\}=\\textsc\{Think\}\(\\mathcal\{S\},\\,C,\\,t\_\{\\text\{err\}\},\\,\\omega\_\{1\},\\dots,\\omega\_\{i\}\)\(2\)whereai∈\{Query,Finish\}a\_\{i\}\\in\\\{\\textsc\{Query\},\\,\\textsc\{Finish\}\\\}\. Ifai=Querya\_\{i\}=\\textsc\{Query\}, the Inspector selects new parameters\(𝝈i\+1,ti\+1start,ti\+1end\)\(\\boldsymbol\{\\sigma\}\_\{i\+1\},\\,t^\{\\text\{start\}\}\_\{i\+1\},\\,t^\{\\text\{end\}\}\_\{i\+1\}\)and retrieves the next snapshotωi\+1\\omega\_\{i\+1\}\. This loop continues until eitherai=Finisha\_\{i\}=\\textsc\{Finish\}or a maximum number of iterationsNNis reached\.

Upon termination, the Inspector produces anInspector Reportℛ\\mathcal\{R\}that summarizes the diagnosed behavioral mismatch between𝒮\\mathcal\{S\}andCC, reasoning on the mismatch, and suggested fixes for the subsequent RTL Debugger\. Note that the testbench is not exposed to the Inspector since the goal of self\-correction should be finding the mismatched behavior between the RTL Code𝒞\\mathcal\{C\}and the functional description𝒮\\mathcal\{S\}instead of the testbench\.

### III\-CRTL Debugger

After receiving the Inspector Reportℛ\\mathcal\{R\}, the RTL Debugger analyzes the buggy RTL codeCCalongside the diagnosed behavioral mismatch and suggested fixes contained inℛ\\mathcal\{R\}\. The Debugger then performs targeted edits to produce a corrected versionC′C^\{\\prime\}\. Rather than attempting to rewrite the entire module, the Debugger focuses on the specific logic blocks identified by the Inspector, preserving the structure of code that is functioning correctly\.

The corrected RTLC′C^\{\\prime\}is re\-simulated\. Letm​\(C\)m\(C\)denote the number of output mismatches for a given RTL implementationCC\. Ifm​\(C′\)<m​\(C\)m\(C^\{\\prime\}\)<m\(C\), the edit is accepted andCCis updated toC′C^\{\\prime\}\. Ifm​\(C′\)≥m​\(C\)m\(C^\{\\prime\}\)\\geq m\(C\), the edit is rolled back to prevent regressions, and the previous version is retained\. This checkpoint is necessary because an edit that resolves one mismatch may introduce others, particularly in sequential circuits where shared state logic has cascading effects\. Requiring monotonic reduction in mismatch count ensures steady forward progress\.

When the accepted edit reduces but does not eliminate all mismatches, the system invokes the Inspector again on the updated codeC′C^\{\\prime\}with the new error timestamp\. This reflects a common pattern in real\-world RTL debugging: a single design may contain multiple independent bugs, or fixing one issue may reveal a previously masked failure\. The Inspector then begins a fresh round of waveform exploration on the updated design, and the cycle repeats\. The full closed\-loop iteration between the Inspector and RTL Debugger continues until eitherm​\(C\)=0m\(C\)=0\(all test cases pass\) or a maximum iteration limitMMis reached\.

## IVExperiment and Result

### IV\-AExperimental Setup

We evaluated VeriTrace on VerilogEval\-V2\[[13](https://arxiv.org/html/2608.02878#bib.bib2),[19](https://arxiv.org/html/2608.02878#bib.bib3)\], a benchmark comprising 156 Verilog coding problems spanning combinational logic and sequential circuits111One of the problems had a mismatched testbench and prompt\. After consulting with the authors of\[[19](https://arxiv.org/html/2608.02878#bib.bib3)\], we made the corresponding adjustments\.\. Each problem includes a natural language specification and a golden testbench\. We report the highest PASS@1 accuracies from the literature\[[10](https://arxiv.org/html/2608.02878#bib.bib1),[37](https://arxiv.org/html/2608.02878#bib.bib4)\]\. For the reproduced and our method, we report withn=3n=3\. This mitigates the sampling variance\.

TABLE II:Comparison on VerilogEval\-V2\.
### IV\-BKey Results

Table[II](https://arxiv.org/html/2608.02878#S4.T2)compares VeriTrace with state\-of\-the\-art open source multi\-agent systems\[[10](https://arxiv.org/html/2608.02878#bib.bib1),[37](https://arxiv.org/html/2608.02878#bib.bib4),[8](https://arxiv.org/html/2608.02878#bib.bib18)\]\. We set N=5 and M=10\. With Claude Sonnet 4\.5\[[2](https://arxiv.org/html/2608.02878#bib.bib10)\], VeriTrace achieves 100% Pass@1, the first system to achieve perfect functional correctness in VerilogEval\-V2, closing the gap that persisted in all prior approaches\. To enable a fair same\-model comparison, we also evaluate with Claude Sonnet 4\.0, where VeriTrace reaches 97\.4% Pass@1, a \+5\.1% improvement over MAGE on the identical backbone \(92\.3%\)222We reproduced MAGE using its open\-source implementation\[[37](https://arxiv.org/html/2608.02878#bib.bib4)\], substituting Claude Sonnet 4\.0 and 4\.5 as versions 3\.5 and 3\.7 have been deprecated\. We note significant performance degradation with Claude Sonnet 4\.5, attributable to fragile testbench syntax and output parsing\.\. This gain is attributable entirely to VeriTrace’s debugging agency, as both systems share the same underlying LLM\.

We also note ACE\-RTL\[[8](https://arxiv.org/html/2608.02878#bib.bib18)\]333ACE\-RTL\[[8](https://arxiv.org/html/2608.02878#bib.bib18)\]reports Agentic Pass Rate \(APR\), defined as the fraction of uniquely solved problems, rather than the statistical Pass@1 estimator used by other entries\. Its implementation is not publicly available\., which reports 95\.5% APR on VerilogEval\-V2 using the same Claude Sonnet 4\.0 backbone and its custom fine\-tuned model\. However, APR measures the fraction of uniquely solved problems across runs rather than the expected single\-attempt pass rate, and its closed\-source implementation precludes reproduction under controlled conditions\. We therefore compare primarily against reproducible open\-source baselines\.

TABLE III:Ablation StudyTABLE IV:Per\-problem ablation on debugging\-intensive problems\.
### IV\-CAblation Studies

#### IV\-C1The Effectiveness of Inspector

To isolate the contribution of the Inspector, we compare VeriTrace with and without this component\. Table[III](https://arxiv.org/html/2608.02878#S4.T3)reports per\-agent and total token consumption, averaged across all problems\. Because LLM API latency introduces variability in wall\-clock time, we report the average number of LLM calls as a proxy for runtime instead\. Pass@1 is computed overn=3n=3runs to reduce sampling variance\. Both configurations are using the Claude Sonnet 4\.5 backbone\[[2](https://arxiv.org/html/2608.02878#bib.bib10)\]with temperaturet=0\.85t=0\.85\.

Both configurations consume comparable tokens during RTL generation, confirming that the Inspector’s benefit arises in the debugging phase rather than initial code generation\. With Inspector, waveform analysis is offloaded to a dedicated agent that produces targeted diagnostic reports, enabling the RTL Debugger to apply more precise fixes\. This specialization reduces combined debugging tokens \(RTL Debugger \+ Inspector\) relative to the RTL Debugger alone without the Inspector, yielding an overall reduction of approximately 18% in total token consumption\. This improvement comes with a trade\-off: due to the nature of iterative inspection, VeriTrace uses more rounds of LLM calls on average, leading to longer runtime\.

#### IV\-C2Analysis on the Hard Problems

To understand which problem categories benefit the most, we further examine the 7 problems that consistently trigger the debugging loop in both configurations \(Table[IV](https://arxiv.org/html/2608.02878#S4.T4)\)\. For combinational and non\-FSM sequential circuits, both systems achieve 100% Pass@1\. The Inspector’s advantage here is primarily efficiency as it reduces debugging tokens in 3 of 4 cases by providing more actionable diagnostic information upfront\.

The contrast is sharpest on FSM problems, where the system without the Inspector achieves only 0–33% Pass@1\. The Inspector’s ability to trace state transitions across time windows allows it to pinpoint root causes in feedback\-heavy designs, boosting all three to 100% Pass@1\. Notably, for Prob155 the Inspector reduces total token consumption by over 5× \(619k → 110k\), demonstrating that accurate diagnosis not only improves correctness but also avoids the wasteful trial\-and\-error cycles of blind retry\. In this case we observed that the RTL Debugger ended up editing the whole module after multiple failed attempts, consuming significantly more tokens\.

## VDiscussion and Limitations

VerilogEval\-V2 comprises 156 single\-module problems with provided golden testbenches\. Industrial designs involve multi\-module hierarchies, incomplete specifications, and far larger signal spaces\. Whether the Inspector’s temporal exploration scales to such settings remains an open question\. Multi\-task benchmarks such as CVDP\[[20](https://arxiv.org/html/2608.02878#bib.bib20),[8](https://arxiv.org/html/2608.02878#bib.bib18),[1](https://arxiv.org/html/2608.02878#bib.bib38)\]would exercise the framework under more diverse conditions\. Because CVDP evaluation requires multiple independent runs per problem with frontier\-model API calls at each iteration, the associated cost is non\-trivial for academic settings\. In preliminary experiments, we applied Agentic Temporal Exploration within a hierarchical multi\-agent framework to two challenging CVDP specification\-to\-RTL problems and solved both, suggesting that the debugging methodology may generalize beyond single\-module benchmarks\. Comprehensive evaluation is planned as follow\-up work\.

The Testbench Agent dumps waveforms for all signals by default, which is what enables the Inspector to query arbitrary internal signals\. Critically, the Inspector does not ingest the full VCD into the LLM context\. Instead, it retrieves only the signals and time windows it selects at each iteration, so token cost scales with diagnostic complexity rather than design size\. For the single\-module problems in VerilogEval\-V2 this storage overhead is negligible, but for industrial\-scale modules with thousands of signals, adaptive waveform dumping or on\-demand re\-simulation may be necessary\.

Finally, as evidenced by the gap between Claude Sonnet 4\.0 \(97\.4%\) and 4\.5 \(100%\), all current multi\-agent RTL systems remain sensitive to the underlying LLM\. Disentangling architectural from model\-level contributions remains a shared challenge\.

## VIConclusion

We presented VeriTrace, a multi\-agent system that introduces Agentic Temporal Exploration, granting LLM agents full control over signal selection and temporal exploration during debugging\. VeriTrace achieves 100% Pass@1 on VerilogEval\-V2, the first perfect score on this benchmark, while reducing token consumption by 18% through more targeted diagnosis\. Our results demonstrate that debugging agency, not just richer feedback, is the key to closing the final accuracy gap in LLM\-based RTL generation\. Future work will extend Agentic Temporal Exploration to multi\-module designs and dynamic agent allocation\. The implementation of VeriTrace will be publicly available\.

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