PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices

# PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices
Source: [https://arxiv.org/html/2608.26113](https://arxiv.org/html/2608.26113)
Deepak Vungarala1, Deniz Najafi1, Abdulrahman Aljoudi2, Zahra Ghanaatian3, Navid Khoshavi4, Gourav Datta5, Arman Roohi6, Mahdi Nikdast3, Shaahin Angizi1 1New Jersey Institute of Technology, USA2University of Michigan, USA3Colorado State University, USA4AMD, USA 5Case Western Reserve, USA6University of Illinois, Chicago, USA E\-mails: \{dv336,shaahin\.angizi\}@njit\.edu

###### Abstract

We presentPICasso, an AI\-assisted framework for automated synthesis, verification, and optimization of photonic integrated circuits \(PICs\) from natural\-language specifications\. PICasso couples a structured NL→\\rightarrowYAML→\\rightarrowGDS generation pipeline with PDK aware knowledge injection, automated placement and routing, DRC/LVS validation, and SAX\-based photonic simulation\. To systematically evaluate AI\-driven photonic design, we introducePIC\-Set, a benchmark of 36 parameterized PIC design tasks spanning core photonic primitives and multi\-component circuits\. Using PIC\-Set, we benchmark several state\-of\-the\-art Large Language Models \(LLMs\) under a unified evaluation protocol, including new metrics such as structural and functionalSpec​@​k\\mathrm\{Spec\}@k, optimization efficiency, and robustness under perturbations\. Across the benchmark, PICasso significantly improves end\-to\-end specification satisfaction compared to vanilla LLM generation\. StructuralSpec​@​3\\mathrm\{Spec\}@3reaches up to 92\.7% and functionalSpec​@​3\\mathrm\{Spec\}@3up to 52% on high\-complexity circuits\. In addition, PICasso consistently reduces circuit insertion loss, lowering the mean loss from 4\.98 dB to 3\.25 dB \(1\.74 dB improvement\) through simulation\-guided optimization\. These results demonstrate that structured domain constraints, physical verification, and simulation feedback transform LLMs from brittle netlist generators into practical PIC design agents capable of producing manufacturable layouts with competitive runtimes relative to manual GUI\-based workflows\.Our code and dataset are released at[https://anonymous\.4open\.science/r/PICasso\-7D52](https://anonymous.4open.science/r/PICasso-7D52)

## IIntroduction

Silicon photonic integrated circuits \(PICs\) underpin emerging applications in optical interconnects, LiDAR, and quantum photonics, with the addressable market projected to exceed $7 billion within five years\[[23](https://arxiv.org/html/2608.26113#bib.bib287)\]\. Yet the design toolchain has not kept pace: circuit complexity is scaling faster than the manual, GUI\-centric workflows that dominate current photonic design automation \(PDA\)\. However, today’s PIC design workflows are fundamentally misaligned with the scale and rigor demanded by this rapid market growth\. Current photonic design automation \(PDA\) tools remain predominantly GUI\-centric\[[18](https://arxiv.org/html/2608.26113#bib.bib296)\], which makes them ill\-suited for the systematic development required when circuits scale to thousands of elements\. Engineers manually draw and wire every component, a process that lacks version control, reproducibility, and the parametric flexibility essential for exploring design space\[[8](https://arxiv.org/html/2608.26113#bib.bib297)\]\[[9](https://arxiv.org/html/2608.26113#bib.bib298)\]\. As circuit complexity increases, this manual approach becomes untenable: placement and routing effort scales super\-linearly, amplifying human error; parametrically defined building blocks for optimization are complex or impossible to express in graphical interfaces; and critically, the design, simulation, and verification stages remain fragmented across incompatible commercial tools \(Lumerical\[[12](https://arxiv.org/html/2608.26113#bib.bib259)\], Ansys\[[11](https://arxiv.org/html/2608.26113#bib.bib261)\]\) and open\-source alternatives \(Scattering Analysis eXtension\-SAX\[[21](https://arxiv.org/html/2608.26113#bib.bib260)\], gdsfactory\[[24](https://arxiv.org/html/2608.26113#bib.bib294)\]\), forcing repeated manual translation that introduces errors and delays time\-to\-market\.

Large Language Models \(LLMs\) are increasingly being applied to hardware design, enabling the generation, optimization, and verification of Hardware Description Language \(HDL\) / High\-Level Synthesis \(HLS\) code\. Works such as VeriGen\[[28](https://arxiv.org/html/2608.26113#bib.bib16)\], ChatEDA\[[33](https://arxiv.org/html/2608.26113#bib.bib17)\], and Autochip\[[29](https://arxiv.org/html/2608.26113#bib.bib237)\]integrate LLMs into RTL\-to\-GDSII flows, automate assertion creation, and leverage simulation feedback for precise code synthesis\. AnalogCoder\[[14](https://arxiv.org/html/2608.26113#bib.bib10)\]and SPICEPilot\[[30](https://arxiv.org/html/2608.26113#bib.bib9)\]pioneer the generation of analog circuits via in\-context learning\. In PIC design, research is sparse: early work generated FDTD scripts for PCSEL simulation\[[15](https://arxiv.org/html/2608.26113#bib.bib284)\], translated natural language into GDSII layouts\[[19](https://arxiv.org/html/2608.26113#bib.bib285)\]\. PIC\-Bench\[[34](https://arxiv.org/html/2608.26113#bib.bib286)\]has recently established the first open\-source benchmark for PIC design, offering 24 canonical circuit design tasks spanning filters, switches, and interconnect devices\.

While such benchmarking efforts represent an important step toward standardizing PIC evaluation, current LLM\-based approaches remain fundamentally limited\. Most rely on heuristic prompt engineering, ad hoc trial\-and\-error workflows, and primitive error\-repair loops that fail to leverage the reasoning capabilities of modern foundation models\. Moreover, existing systems incorporate only minimal domain knowledge, resulting in designs that are often syntactically valid yet physically unrealizable or functionally incorrect\. These limitations motivate three central research questions for the next generation of PDARQ1: To what extent can LLMs generate functionally correct PIC designs when guided by explicit photonic domain knowledge and structured constraints?RQ2: Can device\-level optimization, traditionally a highly manual process, be automated end\-to\-end through LLM\-driven generation and simulation\-guided refinement?RQ3:How can device\- and circuit\-level optimization be unified in a single closed loop to enable research\-grade PIC design with minimal human intervention? To address these questions, we introduce the following contributions in this manuscript\.

\(i\) We proposePICasso, a fully automated LLM\-assisted PIC design framework integrating structured YAML generation, PDK\-aware knowledge injection, pilot validation, DRC/LVS verification, and closed\-loop regeneration\.\(i​i\)\(ii\)We designPIC\-Set, a curated, open\-source dataset comprising over 36 parameterized component\- and circuit\-level design tasks\. \(iii\) We implement an automated two\-stage optimization loop that unifies device\-level geometry tuning with circuit\-level interference control via SAX simulations, representing the first end\-to\-end LLM\-driven optimization flow for PICs\. \(iv\) We propose evaluation metrics: structural and functionalSpec​@​k\\mathrm\{Spec\}@k, optimization efficiency, and use them to benchmark several state\-of\-the\-art LLMs across the full PIC\-Set\.

Together, PIC\-Set and PICasso establish a first\-of\-its\-kind foundation for evaluating and advancing LLM\-driven PIC design\. They demonstrate that, when paired with structured domain constraints and physical verification, modern LLMs can transition from producing sporadically valid designs to reliably generating manufacturable, optimized PICs at scale\.

## IIBackground

LLM for Hardware Design\.Recent studies demonstrate the potential of LLMs for generating HDL and HLS designs\. Frameworks such as VeriGen\[[28](https://arxiv.org/html/2608.26113#bib.bib16)\]and ChatEDA\[[33](https://arxiv.org/html/2608.26113#bib.bib17)\]automate stages of the RTL\-to\-GDSII workflow, while AssertLLM\[[6](https://arxiv.org/html/2608.26113#bib.bib167)\]and UVLLM\[[10](https://arxiv.org/html/2608.26113#bib.bib18)\]leverage specialized LLM pipelines to generate SystemVerilog assertions and automate RTL verification and repair\. LLM\-driven hardware generation and optimization have also been explored in ChipGPT\[[4](https://arxiv.org/html/2608.26113#bib.bib19)\]and AutoChip\[[29](https://arxiv.org/html/2608.26113#bib.bib237)\], where simulation feedback iteratively refines Verilog designs\. Several efforts focus on datasets and design automation frameworks\. TPU\-Gen\[[32](https://arxiv.org/html/2608.26113#bib.bib299)\]and MG\-Verilog\[[36](https://arxiv.org/html/2608.26113#bib.bib20)\]introduce large\-scale datasets for automated hardware generation, while Chip\-Chat\[[3](https://arxiv.org/html/2608.26113#bib.bib238)\], MEV\-LLM\[[25](https://arxiv.org/html/2608.26113#bib.bib21)\], and DeepCircuitX\[[17](https://arxiv.org/html/2608.26113#bib.bib22)\]explore interactive, multi\-expert, and Chain\-of\-Thought–enhanced approaches for RTL generation and early PPA estimation\. Other systems, including RTLLM\[[20](https://arxiv.org/html/2608.26113#bib.bib23)\], GPT4AIGChip\[[7](https://arxiv.org/html/2608.26113#bib.bib8)\], and LLMCompass\[[35](https://arxiv.org/html/2608.26113#bib.bib25)\], further demonstrate improved design productivity and architectural exploration\. Despite these advances, challenges such as prompt optimization, domain\-specific datasets, model fine\-tuning, and hallucinations continue to limit LLM\-based EDA pipelines\[[33](https://arxiv.org/html/2608.26113#bib.bib17)\]\. Consequently, many works rely on in\-context learning \(ICL\) to improve performance\[[5](https://arxiv.org/html/2608.26113#bib.bib26)\]\. In the analog domain, AnalogCoder\[[14](https://arxiv.org/html/2608.26113#bib.bib10)\], SPICEPilot\[[30](https://arxiv.org/html/2608.26113#bib.bib9)\], and Masala\-CHAI\[[2](https://arxiv.org/html/2608.26113#bib.bib27)\]represent early attempts at circuit generation through prompt engineering and ICL, while emerging directions explore LLM\-assisted hardware paradigms such as in\-memory computing with LIMCA\[[31](https://arxiv.org/html/2608.26113#bib.bib283)\]\.

Automating PIC Design\.A substantial body of work has focused on inverse design and related semi\-automated or AI\-based methods for PIC design\[[22](https://arxiv.org/html/2608.26113#bib.bib301),[16](https://arxiv.org/html/2608.26113#bib.bib302),[13](https://arxiv.org/html/2608.26113#bib.bib300)\]\. For example, topology\- and adjoint\-based inverse\-design methods have been shown to explore high\-dimensional device parameter spaces efficiently and yield markedly more compact, higher\-performance photonic devices than conventional forward sweeps\[[27](https://arxiv.org/html/2608.26113#bib.bib291)\]\. In addition, deep\-learning and generative\-model approaches such as convolutional neural networks, autoencoders, and reinforcement\-learning frameworks have recently been applied to the inverse design of silicon photonic devices, enabling rapid mapping from target optical functionality to geometry\[[1](https://arxiv.org/html/2608.26113#bib.bib292)\]\. Further advancing the automation frontier, coupled device\-level and layout\-level frameworks integrate fabrication\-aware inverse\-design engines with automated placement and routing \(PnR\) tools, thereby lowering human intervention and improving scalability of PIC workflows\[[37](https://arxiv.org/html/2608.26113#bib.bib293)\]\. Collectively, these semi\-automated pipelines demonstrate that AI\-driven, simulation\-based loops can reduce manual expert tuning and enable broader exploration of design space, thus promising more autonomous PIC design systems\.

Research on applying LLMs to PIC design remains scarce, with only a few preliminary studies addressing this area\. The use of LLMs to generate FDTD scripts for simulating a photonic crystal surface\-emitting laser \(PCSEL\) structure, followed by AI\-based optimization of the device parameters, has been shown in\[[15](https://arxiv.org/html/2608.26113#bib.bib284)\]\. However, their workflow was not fully autonomous, relying heavily on expert intervention to define specifications and correct coding errors iteratively\. Liu et al\.\[[19](https://arxiv.org/html/2608.26113#bib.bib285)\]introduced an automated pipeline capable of translating natural\-language descriptions into Python code for generating GDSII layouts via an open\-source library\. While promising, their evaluation was limited to seven relatively simple devices, leaving questions about scalability and generalization to more complex designs\. The most promising work, i\.e\., PIC\-Bench\[[34](https://arxiv.org/html/2608.26113#bib.bib286)\], introduced an open\-source benchmark for PIC design, comprising 24 distinct photonic integrated circuit design problems\. The framework was assessed using state\-of\-the\-art commercial LLMs and demonstrated relatively acceptable syntax correctness rates; however, the functionality outcomes were highly unsatisfactory\. With certain restrictions applied, Gemini 1\.5 Pro’s functionality score improved from 8\.33% to 21\.67% in Pass@1, and from 12\.50% to 37\.50% in Pass@5 at best\.

![Refer to caption](https://arxiv.org/html/2608.26113v1/x1.png)Figure 1:Picasso Framework\.
## IIIPICasso

ThePICassoframework \(Fig\.[1](https://arxiv.org/html/2608.26113#S2.F1)\) provides an automated, constraint\-driven synthesis pipeline that maps high\-level photonic intent to manufacturable, PDK\-compliant layouts\. Its design is anchored in two core principles: \(i\)*prompt\-constrained generation*, where the LLM receives a structured, domain\-informed specification that restricts its output space to valid photonic circuits, and \(ii\)*feedback\-driven refinement*, where syntactic, semantic, and physical violations are automatically identified and translated into corrective constraints for iterative regeneration\. Together, these mechanisms bridge the gap between natural\-language circuit descriptions and physically verifiable photonic implementations\. A summary of quantitative evaluation metrics used throughout the pipeline is provided in Sec\.[IV](https://arxiv.org/html/2608.26113#S4)\.

### III\-AFramework

From Fig\.[1](https://arxiv.org/html/2608.26113#S2.F1)the synthesis process begins with a user\-defined description of circuit functionality, interconnections, and optional performance goals such as insertion loss or splitting ratio1\. This specification is augmented by a*knowledge injection module*2, which supplies the LLM with formal YAML grammar rules, valid component and port definitions from the target PDK, admissible parameter sets obtained viainspect\.signature, spacing requirements, and a curated library of canonical design examples\. The injection also enumerates common failure modes—such as illegal port names, invalid MMI parameters, and insufficient spacing—thereby constraining the LLM to generate foundry\-compatible netlists rather than free\-form layouts\.

A dedicated*pilot prompt*3performs pre\-execution validation on each generated YAML file\. This validator enforces strict ASCII\-only formatting, YAML schema compliance, correct parameter usage, port name consistency, adherence to minimum spacing rules, and the completeness of placement and routing directives\. Any violations encountered at this stage are extracted, distilled into concise diagnostic messages, and appended to the pilot prompt4, forming an adaptive repair loop that persists across the local synthesis run while maintaining readability and prompt stability\.

Once the YAML netlist satisfies pilot validation, it is compiled usinggf\.read\.from\_yaml\(\)5, which instantiates all components, performs geometric placement, and invokes gdsfactory’s auto\-routing engine\. The router generates fabrication\-feasible waveguide paths that respect bend\-radius limits, cross\-section constraints, and PDK\-defined spacing rules, leveraging systematic handling of Euler bends, tapers, straight segments, and Manhattan routing primitives\. The resulting layout is then subjected to two forms of physical verification\. A*design rule check*\(DRC\)6evaluates width, spacing, enclosure, and curvature constraints using thegeneric\_techPDK and KLayout’s rule engine\. When computationally tractable, a*layout\-versus\-schematic*\(LVS\) comparison verifies connectivity consistency between the layout\-extracted netlist and the original YAML, preventing missing or shorted waveguides\. Any DRC or LVS violations generate structured feedback that is returned to the pilot mechanism7, guiding targeted corrections for subsequent LLM generations\.

Designs that pass physical validation enter the*optimization stage*8, where device\-level geometry tuning and circuit\-level phase and coupling refinement are performed\. PICasso employs SAX\-based simulations to evaluate optical performance, enabling optimization toward lower insertion loss, improved balance, and enhanced functional fidelity\. The finalized outputs include an optimized YAML schematic, the corresponding GDS layout, and performance metadata used in Sec\.[IV](https://arxiv.org/html/2608.26113#S4)\. This closed\-loop synthesis–validation–optimization pipeline enables rapid, minimally supervised generation of manufacturable photonic circuits, establishing a scalable foundation for next\-generation photonic EDA workflows\.

As summarized in Table[I](https://arxiv.org/html/2608.26113#S3.T1), prior LLM\-driven PIC design frameworks remain constrained in several critical ways\. PICBench operates exclusively at the netlist level and provides no physical verification or layout generation, while PhIDO introduces NL\-to\-layout generation but lacks end\-to\-end DRC/LVS validation, cannot support large multi\-stage circuits such as AWGs or WDM networks, and does not integrate device\- or circuit\-level optical optimization\. In contrast,PICassois the first unified framework that couples \(i\) a structured NL→\\rightarrowYAML generation pipeline with PDK\-aware constraints, \(ii\) automated placement, routing, and full physical verification, and \(iii\) spectrum\-driven device and circuit optimization within a single closed loop\. This enablesPICassoto reliably handle all 36 tasks in PIC\-Set, including 12 circuits previously unsupported by prior methods and to deliver manufacturable GDSII layouts with substantial improvements in functional Spec@*k*\. These distinctions establishPICassoas the first end\-to\-end autonomous PIC synthesis system rather than a netlist generator or layout assistant, closing longstanding gaps in both robustness and physical correctness\.

![Refer to caption](https://arxiv.org/html/2608.26113v1/x2.png)Figure 2:Data point structure\.TABLE I:Comparison ofPICassowith prior LLM\-based PIC design frameworks\.
### III\-BPIC\-Set: A Curated PIC Benchmark

To enable standardized evaluation and fair comparison of photonic design methodologies, we introducePIC\-Set, a curated benchmark of representative silicon–photonic circuits constructed under a unified technology and simulation stack\. The dataset emphasizes realistic design scenarios and objective diversity, covering widely used photonic primitives such as MMIs, directional couplers, phase shifters, Y\-branches, and waveguide tapers that frequently appear in modulators, WDM filters, and switching fabrics\.

All circuit instances are programmatically instantiated using a parameterized layout generator to ensure consistent parameter ranges, layout conventions, and PDK assumptions\. Each entry includes a literature\-derived target loss budget \(e\.g\.,∼1\.3​dB\\sim 1\.3\\,\\mathrm\{dB\}for ring add\-drop filters,∼2\.2​dB\\sim 2\.2\\,\\mathrm\{dB\}for 16\-channel AWGs, and∼0\.7​dB\\sim 0\.7\\,\\mathrm\{dB\}for2×22\\times 2thermo\-optic switches\), providing meaningful operating points for evaluating layout correctness and optimization performance \(Fig\.[2](https://arxiv.org/html/2608.26113#S3.F2)\)\.

To prevent information leakage across parametrically similar circuits, the dataset is partitioned at the*topology*level into design, validation, and test splits\. Each topology includes machine\-readable YAML netlists, reference GDS/OASIS layouts, parameter bounds, structural constraints, when applicable—SPICE or S\-parameter models\. In addition,PIC\-Setprovides a component library with empirically grounded nominal losses for waveguides, MMIs, and directional couplers, enabling consistent evaluation across synthesis pipelines\. Representative circuits and applications are summarized in Table[II](https://arxiv.org/html/2608.26113#S3.T2)\.

TABLE II:Representative entries fromPIC\-Set\.
### III\-COptimization Framework

PICasso incorporates a two\-tier optimization strategy to improve both device\-level performance and circuit\-level transmission behavior\. This separation ensures that local component refinements and global interference effects are treated distinctly but cohesively\. Device\-Level Optimization\.At the device level, geometry and material parameters are adjusted to match target performance characteristics drawn from empirical measurements or PDK specifications\. Parameters such as waveguide width and radius, MMI dimensions, and heater lengths are swept within physically realizable ranges\. Analytical attenuation models and SAX\-based S\-parameter simulations estimate component\-level losses and coupling behavior\. The optimization seeks parameter vectors𝐱\\mathbf\{x\}that minimize the deviation between simulated responses and target characteristics:

min𝐱⁡‖𝐟​\(𝐱\)−𝐟target‖22,\\min\_\{\\mathbf\{x\}\}\\;\\big\\\|\\mathbf\{f\}\(\\mathbf\{x\}\)\-\\mathbf\{f\}\_\{\\mathrm\{target\}\}\\big\\\|\_\{2\}^\{2\},\(1\)where𝐟​\(⋅\)\\mathbf\{f\}\(\\cdot\)denotes the simulated optical response \(e\.g\., insertion loss or coupling ratio\)\. The result is a device configuration that adheres more closely to expected foundry behavior\. Circuit\-Level Optimization\.At the circuit level, the full PIC is optimized using the SAX simulator\. Phase shifts and coupling coefficients across the layout are treated as tunable variables that shape multi\-path interference\. PICasso employs a multi\-start Nelder–Mead procedure with several random initializations to avoid shallow local minima\. The objective minimizes insertion loss by maximizing the squared dominant singular valueσ12​\(T\)\\sigma\_\{1\}^\{2\}\(T\)of the circuit transfer matrixTT:

minϕ−σ12​\(T​\(ϕ\)\),\\min\_\{\\bm\{\\phi\}\}\\;\-\\sigma\_\{1\}^\{2\}\(T\(\\bm\{\\phi\}\)\),\(2\)whereϕ\\bm\{\\phi\}includes all tunable phases and coupler settings\. This criterion drives the circuit toward maximal throughput while preserving its functional mapping\.

## IVEvaluation Metrics

Existing PIC benchmarks rely on binary pass/fail or syntax\-only correctness\[[34](https://arxiv.org/html/2608.26113#bib.bib286)\], which conflate structural plausibility with physical manufacturability and cannot capture the graded improvements that a multi stage pipeline like PICasso produces\. We therefore define three metrics that jointly quantify correctness, physical validity, and optimization quality across the full synthesis–verification–optimization loop\. PICasso introduces a set of evaluation metrics designed to quantify correctness, physical validity, and optimization quality for automatically generated photonic circuits\. These metrics capture structural validity, functional behavior, and robustness under optimization, thereby enabling consistent comparison across PDKs, circuit topologies, and LLM backends\.

Structural Specification Satisfaction\.The first metric measures whether a generated circuit satisfies all*structural*constraints imposed by the YAML DSL, the PDK, and the layout engine\. A design is considered structurally valid if it satisfies the following conditions: \(i\) the YAML specification parses without error, \(ii\) the resulting component compiles throughgf\.read\.from\_yaml\(\), \(iii\) automated routing completes successfully, and \(iv\) the final GDS passes all DRC checks under thegeneric\_techrule deck\. Layout\-versus\-schematic checks are included when netlist extraction is tractable\. We define structural specification satisfaction at sampling depthkkas

Spec​\_​struct​@​k=1−\(n−csk\)\(nk\),\\vskip\-4\.49997pt\\mathrm\{Spec\}\\\_\{\\mathrm\{struct\}\}@k=1\-\\frac\{\\binom\{n\-c\_\{s\}\}\{k\}\}\{\\binom\{n\}\{k\}\},\(3\)wherennis the number of samples andcsc\_\{s\}is the number of structurally valid designs\. This formulation penalizes methods that frequently violate physical or syntactic rules, while still permitting comparison across circuits of varying complexity\.

Functional Specification Satisfaction\.For designs that pass structural checks, PICasso evaluates whether the resulting circuit satisfies the intended photonic functionality using SAX\-based frequency\-domain simulation\. Functional criteria include power transfer, insertion loss trends, wavelength selectivity, and, when applicable, switching or splitting ratios\. A design passes functional validation if its simulated behavior lies within topology\-specific tolerances derived fromPIC\-Set\. We define functional specification satisfaction as

Spec​\_​full​@​k=1−\(n−cfk\)\(nk\),\\vskip\-3\.99994pt\\mathrm\{Spec\}\\\_\{\\mathrm\{full\}\}@k=1\-\\frac\{\\binom\{n\-c\_\{f\}\}\{k\}\}\{\\binom\{n\}\{k\}\},\(4\)wherecfc\_\{f\}counts the number of designs that satisfy both structural and functional requirements\. This metric distinguishes PICasso from baseline LLM outputs, which seldom meet functional objectives despite occasional syntactic correctness\.

Optimization Efficiency\.Optimization effectiveness is evaluated by measuring the normalized reduction in insertion loss between the initial layout and the optimized configuration\. LetI​LbeforeIL\_\{\\mathrm\{before\}\}andI​LafterIL\_\{\\mathrm\{after\}\}denote the insertion loss before and after optimization\. We defineηopt=I​Lbefore−I​LafterI​Lbefore\+ε\\eta\_\{\\mathrm\{opt\}\}=\\frac\{IL\_\{\\mathrm\{before\}\}\-IL\_\{\\mathrm\{after\}\}\}\{IL\_\{\\mathrm\{before\}\}\+\\varepsilon\}, whereε\\varepsilonis whereε=10−6\\varepsilon=10^\{\-6\}prevents division by near\-zero denominators\. used to avoid division by arbitrarily small denominators\. The metric is clipped to the interval\[0,1\]\[0,1\]and averaged across all circuits that pass structural validation\. This reflects the gain attributable to PICasso’s device\- and circuit\-level tuning\.

TABLE III:Aggregate Spec@k performance across all 36 PIC\-Set tasks\.
## VExperiment results

Setup\.Evaluation follows a two\-phase protocol\. Phase 1 \(vanilla\) runs each LLM with no structural priors, routing constraints, or optimization, measuring inherent generation capability\. Phase 2 \(framework\) activates the full PICasso pipeline: schema checking, DRC/LVS enforcement, SAX\-based functional evaluation, and two\-stage optimization\. For each of the 36 PIC\-Set tasks, five samples are drawn per phase\(180 samples per model per phase\)\. Complexity tiers follow the three\-level taxonomy defined in Sec\.[III\-B](https://arxiv.org/html/2608.26113#S3.SS2): C1 \(single\-component\), C2 \(2–8 components\), C3 \(\>\>8 components\)\.

For fair comparison to prior literature, the 24 PICBench compatible tasks form a secondary benchmark subset\. Because existing frameworks differ substantially in their input/output representations, physical validation scope, and simulation stacks, direct numerical comparison is inappropriate\. Instead, a capability\-level comparison is provided in Table[IV](https://arxiv.org/html/2608.26113#S5.T4), and focuses on design\-space coverage, representation, automation, and runtime\.

Results and Analysis\.Results are reported usingSpec@​k\\text\{Spec@\}kmetrics, which reflect end\-to\-end specification satisfaction\.The metric,Spec@1\_structuralreports the probability that the top\-1 sample satisfies structural constraints, whileSpec@3\_structuralmeasures correctness across the best of 3\.Spec@1\_fullandSpec@3\_fulladditionally require functional correctness\. This is stricter than prior work, as it accounts for both physical\-level \(DRC/LVS\) and reflects final post\-optimization behavior\.

![Refer to caption](https://arxiv.org/html/2608.26113v1/x3.png)Figure 3:Comparison between Vanilla LLM and PICasso on \(a\) MZI \(b\) MZM layout generation\.Table[III](https://arxiv.org/html/2608.26113#S4.T3)reports aggregate results across all 36 PIC\-Set tasks for three state\-of\-the\-art LLMs: GPT\-4o, Claude Sonnet 4\.5, and Llama 3\.1 70B\. Results are reported for both vanilla generation and the full PICasso pipeline\.

Across all models and complexity tiers, PICasso substantially improves satisfaction with structural and functional specifications\. For example, GPT\-4o achieves structuralSpec​@​3\\mathrm\{Spec\}@3of99\.2%99\.2\\%on medium\-complexity circuits under PICasso, compared to33\.3%33\.3\\%under vanilla generation\. Claude Sonnet 4\.5 shows the strongest performance, achieving100%100\\%structuralSpec​@​3\\mathrm\{Spec\}@3and100%100\\%functionalSpec​@​3\\mathrm\{Spec\}@3on Complexity\-2 tasks\. Even for large circuits in Complexity\-3, PICasso improves structuralSpec​@​3\\mathrm\{Spec\}@3to90\.7%90\.7\\%and functionalSpec​@​3\\mathrm\{Spec\}@3to52\.0%52\.0\\%, whereas vanilla LLM generation fails to produce functionally correct designs\.

Overall, the results indicate that PICasso transforms LLMs from unreliable circuit generators into practical PIC design agents capable of producing manufacturable layouts that satisfy both physical and functional constraints\.

A cross\-framework comparison \(Table[IV](https://arxiv.org/html/2608.26113#S5.T4)\) highlights qualitative differences among PICBench, PhIDO, and PICasso\. PICBench supports 24 netlist\-only tasks and evaluates frequency\-domain behavior but lacks layout or DRC/LVS capabilities\. PhIDO extends this to multi\-agent NL\-to\-layout generation but supports fewer physical checks and cannot handle AWG, WDM, or large multi\-stage circuits\. PICasso supports 36 tasks, including 12 circuits that were previously unsupported, and integrates full physical validation, spectral evaluation, and optimization\. Despite deeper validation, the runtime remains competitive with prior multi\-agent frameworks due to targeted repair and parallelized checking\. PICasso therefore establishes the first end\-to\-end autonomous PIC synthesis framework capable of natural\-language input, structured multilayer validation, and functional optimization, with demonstrated improvements across diverse LLM families\. The results indicate that architectural priors, validation\-loop feedback, and physical\-level constraints are crucial for PIC code generation and cannot be achieved solely through prompting\.

TABLE IV:Experiment runtime comparison\.- 1“Human Designer” refers to a trained PIC engineer implementing the same tasks in a commercial photonic design GUI \(e\.g\., IPKISS, Nazca, KLayout\+GDSFactory PCells\)\. PICasso achieves full\-stack verification and supports higher\-complexity circuits while eliminating virtually all manual effort\.

### V\-AOptimization analysis

Fig\.[4](https://arxiv.org/html/2608.26113#S5.F4)reports the initial optical insertion loss achieved by vanilla LLM\-based circuit generation and by the proposedPICassoframework, prior to any explicit optimization\. The figure is constructed from pooled summary statistics computed over all circuits that successfully build and pass structural validation across five LLM back\-ends \(claude\-sonnet\-4\.5, deepseek\-r1\-api, gpt\-4o, llama\-3\.1\-70b, and qwen\-2\.5\-32b\)\.

![Refer to caption](https://arxiv.org/html/2608.26113v1/x4.png)Figure 4:Initial Loss Comparison: Vanilla vs PICasso \(N​\_​VN\\\_V= 48,N​\_​PN\\\_P= 158\)\.The underlying data originate from the optimization, which record the pre\- and post\-optimization losses for each generated circuit\. To ensure a fair comparison, we apply identical filtering criteria to the vanilla andPICassophases: \(i\) only samples withstructural\_pass = trueare retained, meaning the circuit can be instantiated from the generated YAML and passes DRC checks; \(ii\) we require that a YAML or GDS file is available so that loss can be evaluated; \(iii\) we restrict to models that have at least one vanilla and onePICassosample after filtering\. After these steps, we obtain4848valid vanilla circuits and158158validPICassocircuits \(206 circuits in total\)\. Let𝒱\\mathcal\{V\}and𝒫\\mathcal\{P\}denote the sets of valid vanilla andPICassosamples, respectively, and letLbeforecircL^\{\\text\{circ\}\}\_\{\\mathrm\{before\}\}andLbeforetotL^\{\\text\{tot\}\}\_\{\\mathrm\{before\}\}denote the initial circuit and total insertion loss in decibels\. We pool all samples across models and compute population\-level statistics for each phase: the mean and median initial circuit loss for vanilla andPICasso, as well as the mean initial total loss\. The improvement shown in Fig\.[4](https://arxiv.org/html/2608.26113#S5.F4)is defined as the difference between phases,Δ=Vanilla−PICasso\\Delta=\\text\{Vanilla\}\-\\text\{\{PICasso\}\}, soΔ\>0\\Delta\>0indicates thatPICassoyields lower loss\.

Numerically, the pooled mean initial circuit loss decreases from4\.984\.98dB for vanilla to3\.253\.25dB forPICasso, corresponding to an average improvement of1\.741\.74dB\. The median initial circuit loss drops from6\.856\.85dB to0\.720\.72dB, a6\.136\.13dB reduction that reflects the large number ofPICasso\-generated circuits with near\-zero insertion loss\. Because device loss is0dB for both phases in this analysis, the mean initial total loss matches the circuit\-loss statistics and also improves by1\.741\.74dB\. Taken together, Fig\.[4](https://arxiv.org/html/2608.26113#S5.F4)shows that, among circuits that successfully build and pass structural checks, thePICassoframework consistently produces higher\-quality initial photonic circuits with substantially lower optical insertion loss across all five LLM models\.

Execution time comparison\.To highlight the additional capabilities of our framework and its minimal human\-effort requirements, we compare execution times across prior approaches\. As shown in Table[IV](https://arxiv.org/html/2608.26113#S5.T4), PICasso achieves full\-stack verification and supports higher\-complexity circuits while maintaining competitive runtimes\. Despite performing deeper pipeline steps than netlist\- or schematic\-level baselines, PICasso completes tasks in 4–8 minutes, substantially faster than manual GUI\-based design workflows, which require 25–60 minutes\.

### V\-BDemonstration of PICasso

Table[V](https://arxiv.org/html/2608.26113#S5.T5)isolates the contribution of each PICasso stage on 12 representative PIC\-Set tasks \(Claude Sonnet 4\.5,n=5n\{=\}5, Spec@5\)\. Raw and knowledge\-injected generation \(Baseline, V1–V2\) reaches at most 25–42% structural correctness and zero functional Spec@5, as LLM output routinely fails port\-consistency and routing checks before reaching the layout engine\. Pilot validation \(V3\) alone saturates structural correctness at 100% across all tiers; physical and functional verification \(V4\) then raises full\-specification Spec@5 from 0% to 91\.7%, with device\- and circuit\-level optimisation \(V5, full PICasso\) yielding 83\.3%—consistent with the aggregate gains in Table[III](https://arxiv.org/html/2608.26113#S4.T3)\. The 64\-QAM Modulator \(C3\) and 90∘Optical Hybrid \(C2\) achieve 100% structural correctness under V5 but zero functional Spec@5, as their phase\-matching constraints exceed the convergence radius of the Nelder–Mead optimizer; improving optimizer scope for high\-dimensional photonic circuits remains an open direction\.

TABLE V:PICasso pipeline contribution on 12 PIC\-Set tasks \(Claude Sonnet 4\.5,n=5n\{=\}5, Spec@5\)\.

## VIConclusion

This work introducedPICasso, an end\-to\-end LLM\-driven framework for autonomous PIC synthesis, verification, and optimization, together withPIC\-Set, a curated benchmark of 36 parameterized silicon\-photonic design tasks\. By coupling a PDK\-aware NL→\\rightarrowYAML→\\rightarrowGDS pipeline with DRC/LVS checks, SAX\-based simulation, and a two\-stage optimization loop, PICasso reliably generates manufacturable layouts from natural\-language intent\. The proposed metrics, structural and functionalSpec​@​k\\mathrm\{Spec\}@kand optimization efficiency, enable rigorous, reproducible evaluation across models, topologies, and complexity tiers\. Experiments across GPT\-4o, Claude Sonnet 4\.5, and Llama 3\.1 70B demonstrate that PICasso raises full\-specSpec​@​3\\mathrm\{Spec\}@3from 0% to up to 52% on high\-complexity circuits, achieves 100% structural and functionalSpec​@​3\\mathrm\{Spec\}@3on Complexity 1 and 2 under Claude Sonnet 4\.5, and reduces mean insertion loss from 4\.98 dB to 3\.25 dB \(1\.74 dB improvement\) all within 4–8 minutes per task versus 25–60 minutes for manual GUI\-based workflows\.Remaining limitations include functional failures on phase\-sensitive high\-complexity circuits \(e\.g\., 64\-QAM, 90∘hybrid\) where Nelder–Mead convergence is insufficient; extending the optimizer to gradient\-based or learned surrogate methods is the primary open direction\.

## References

- \[1\]\(2025\)Recent advances in the inverse design of silicon photonic devices and related platforms using deep generative models\.PeerJ Computer Science11,pp\. e2895\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p2.1)\.
- \[2\]J\. Bhandariet al\.\(2025\)Masala\-chai: a large\-scale spice netlist dataset for analog circuits by harnessing ai\(Website\)External Links:[Link](https://arxiv.org/abs/2411.14299)Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[3\]J\. Blocklove, S\. Garg, R\. Karri, and H\. Pearce\(2023\)Chip\-chat: challenges and opportunities in conversational hardware design\.In2023 ACM/IEEE 5th Workshop on Machine Learning for CAD \(MLCAD\),pp\. 1–6\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[4\]K\. Changet al\.\(2023\)Chipgpt: how far are we from natural language hardware design\.arXiv preprint arXiv:2305\.14019\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[5\]D\. Daiet al\.\(2022\)Why can gpt learn in\-context? language models implicitly perform gradient descent as meta\-optimizers\.arXiv preprint arXiv:2212\.10559\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[6\]W\. Fang, M\. Li, M\. Li, Z\. Yan, S\. Liu, H\. Zhang, and Z\. Xie\(2024\)AssertLLM: generating and evaluating hardware verification assertions from design specifications via multi\-llms\.arXiv preprint arXiv:2402\.00386\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[7\]Y\. Fuet al\.\(2023\)Gpt4aigchip: towards next\-generation ai accelerator design automation via large language models\.In2023 IEEE/ACM International Conference on Computer Aided Design \(ICCAD\),pp\. 1–9\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[8\]X\. Gao, M\. Liu, D\. Z\. Pan, and Y\. Lin\(2021\)Interactive analog layout editing with instant placement legalization\.In2021 58th ACM/IEEE Design Automation Conference \(DAC\),Vol\.,pp\. 1249–1254\.External Links:[Document](https://dx.doi.org/10.1109/DAC18074.2021.9586234)Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[9\]X\. Gao, H\. Zhang, M\. Liu, L\. Shen, D\. Z\. Pan, Y\. Lin, R\. Wang, and R\. Huang\(2023\)Interactive analog layout editing with instant placement and routing legalization\.IEEE Transactions on Computer\-Aided Design of Integrated Circuits and Systems42\(3\),pp\. 698–711\.External Links:[Document](https://dx.doi.org/10.1109/TCAD.2022.3190234)Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[10\]Y\. Huet al\.\(2024\)Uvllm: an automated universal rtl verification framework using llms\.arXiv preprint arXiv:2411\.16238\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[11\]A\. Inc\.\(2025\)ANSYS multiphysics simulation software\.Note:ANSYS Inc\., Canonsburg, PA, USA\. Available at:[https://www\.ansys\.com](https://www.ansys.com/)Version 2025 R1Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[12\]A\. Inc\.\(2025\)Lumerical photonic design suite\.Note:[https://www\.lumerical\.com](https://www.lumerical.com/)Version \[specify version used, e\.g\., 2023 R2\]Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[13\]M\. U\. Khan, Y\. Xing, Y\. Ye, and W\. Bogaerts\(2019\)Photonic integrated circuit design in a foundry\+ fabless ecosystem\.IEEE Journal of Selected Topics in Quantum Electronics25\(5\),pp\. 1–14\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p2.1)\.
- \[14\]Y\. Laiet al\.\(2024\)Analogcoder: analog circuit design via training\-free code generation\.arXiv preprint arXiv:2405\.14918\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[15\]R\. Li, C\. Zhang, S\. Mao, H\. Huang, M\. Zhong, Y\. Cui, X\. Zhou, F\. Yin, S\. Theodoridis, and Z\. Zhang\(2023\-08\)From English to PCSEL: LLM helps design and optimize photonic crystal surface emitting lasers\.Note:14 pages, 9 graphicsExternal Links:[Link](https://hal.science/hal-04175312),[Document](https://dx.doi.org/10.48550/arXiv.2104.12145)Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p3.1)\.
- \[16\]R\. Li, C\. Zhang, W\. Xie, Y\. Gong, F\. Ding, H\. Dai, Z\. Chen, F\. Yin, and Z\. Zhang\(2023\)Deep reinforcement learning empowers automated inverse design and optimization of photonic crystals for nanoscale laser cavities\.Nanophotonics12\(2\),pp\. 319–334\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p2.1)\.
- \[17\]Z\. Liet al\.\(2025\)Deepcircuitx: a comprehensive repository\-level dataset for rtl code understanding, generation, and ppa analysis\.arXiv preprint arXiv:2502\.18297\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[18\]B\. Liu, H\. Zhang, X\. Gao, Z\. Kong, X\. Tang, Y\. Lin, R\. Wang, and R\. Huang\(2025\)LayoutCopilot: an llm\-powered multiagent collaborative framework for interactive analog layout design\.IEEE Transactions on Computer\-Aided Design of Integrated Circuits and Systems44\(8\),pp\. 3126–3139\.External Links:[Document](https://dx.doi.org/10.1109/TCAD.2025.3529805)Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[19\]J\. Liu, A\. Sharma, C\. Doumbia, and J\. K\. Poon\(2024\)Towards large\-language model assisted layout of silicon photonic integrated circuits\.InEuropean Conference on Integrated Optics,pp\. 441–447\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p3.1)\.
- \[20\]Y\. Luet al\.\(2024\)Rtllm: an open\-source benchmark for design rtl generation with large language model\.In2024 29th Asia and South Pacific Design Automation Conference \(ASP\-DAC\),pp\. 722–727\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[21\]A\. Lukaszewicz and W\. Bogaerts\(2023\)SAX: scalable circuit modeling for photonic design\.Zenodo\.External Links:[Document](https://dx.doi.org/10.5281/zenodo.7149361),[Link](https://doi.org/10.5281/zenodo.7149361)Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[22\]B\. MacLellan, P\. Roztocki, J\. Belleville, L\. Romero Cortés, K\. Ruscitti, B\. Fischer, J\. Azaña, and R\. Morandotti\(2024\)Inverse design of photonic systems\.Laser & Photonics Reviews18\(5\),pp\. 2300500\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p2.1)\.
- \[23\]MarketsandMarkets\(2025\)Silicon Photonics Market by Product, Components \- Global Forecast to 2030\.Note:[https://www\.marketsandmarkets\.com/Market\-Reports/silicon\-photonics\-116\.html](https://www.marketsandmarkets.com/Market-Reports/silicon-photonics-116.html)\[Accessed: 20\-October\-2025\]Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[24\]J\. Matres and G\. Contributors\(2025\)GDSFactory: Python\-Based Photonic and Analog Chip Design Automation\.Note:[https://gdsfactory\.github\.io/gdsfactory/](https://gdsfactory.github.io/gdsfactory/)Version 9\.x\. Accessed: 2025\-11\-11Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p1.1)\.
- \[25\]B\. Nadimi and H\. Zheng\(2024\)A multi\-expert large language model architecture for verilog code generation\.arXiv preprint arXiv:2404\.08029\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[26\]A\. Sharma, Y\. Fu, V\. Ansari, R\. Iyer, F\. Kuang, K\. Mistry, R\. I\. Aishy, S\. Ahmad, J\. Matres, D\. R\. Englund,et al\.\(2025\)AI agents for photonic integrated circuit design automation\.arXiv preprint arXiv:2508\.14123\.Cited by:[TABLE I](https://arxiv.org/html/2608.26113#S3.T1.6.6.7.1.3.1.1.1),[TABLE IV](https://arxiv.org/html/2608.26113#S5.T4.4.4.4.4)\.
- \[27\]R\. Shen, B\. Hong, X\. Ren, F\. Yang, W\. Chu, H\. Cai, and W\. Huang\(2024\)Recent progress on inverse design for integrated photonic devices: methodology and applications\.Journal of Nanophotonics18\(1\),pp\. 010901–010901\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p2.1)\.
- \[28\]S\. Thakuret al\.\(2024\)Verigen: a large language model for verilog code generation\.ACM Transactions on Design Automation of Electronic Systems29\(3\),pp\. 1–31\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[29\]S\. Thakur, J\. Blocklove, H\. Pearce, B\. Tan, S\. Garg, and R\. Karri\(2023\)Autochip: automating hdl generation using llm feedback\.arXiv preprint arXiv:2311\.04887\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[30\]D\. Vungaralaet al\.\(2024\)Spicepilot: navigating spice code generation and simulation with ai guidance\.arXiv preprint arXiv:2410\.20553\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[31\]D\. Vungarala, M\. H\. Amin, P\. Mercati, A\. Ghosh, A\. Roohi, R\. Zand, and S\. Angizi\(2025\)LIMCA: llm for automating analog in\-memory computing architecture design exploration\.arXiv preprint arXiv:2503\.13301\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[32\]D\. Vungarala, M\. E\. Elbtity, K\. Pandit, S\. Syed, S\. Alam, A\. Ghosh, R\. Zand, and S\. Angizi\(2025\)TPU\-gen: llm\-driven custom tensor processing unit generator\.In2025 IEEE International Conference on LLM\-Aided Design \(ICLAD\),Vol\.,pp\. 1–8\.External Links:[Document](https://dx.doi.org/10.1109/ICLAD65226.2025.00010)Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[33\]H\. Wuet al\.\(2024\)Chateda: a large language model powered autonomous agent for eda\.IEEE Transactions on Computer\-Aided Design of Integrated Circuits and Systems\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[34\]Y\. Wu, X\. Yu, H\. Chen, Y\. Luo, Y\. Tong, and Y\. Ma\(2025\)PICBench: benchmarking llms for photonic integrated circuits design\.In2025 Design, Automation & Test in Europe Conference \(DATE\),pp\. 1–6\.Cited by:[§I](https://arxiv.org/html/2608.26113#S1.p2.1),[§II](https://arxiv.org/html/2608.26113#S2.p3.1),[TABLE I](https://arxiv.org/html/2608.26113#S3.T1.6.6.7.1.2.1.1.1),[§IV](https://arxiv.org/html/2608.26113#S4.p1.1),[TABLE IV](https://arxiv.org/html/2608.26113#S5.T4.1.1.1.2)\.
- \[35\]H\. Zhanget al\.\(2024\)Llmcompass: enabling efficient hardware design for large language model inference\.In2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture \(ISCA\),pp\. 1080–1096\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[36\]Y\. Zhanget al\.\(2024\)MG\-Verilog: Multi\-grained Dataset Towards Enhanced LLM\-assisted Verilog Generation\.In2024 IEEE LLM Aided Design Workshop \(LAD\),Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p1.1)\.
- \[37\]H\. Zhou, P\. Ma, and J\. Gu\(2025\)Toward intelligent electronic\-photonic design automation for large\-scale photonic integrated circuits: from device inverse design to physical layout generation\.InOptical Design Automation,Vol\.13601,pp\. 69–78\.Cited by:[§II](https://arxiv.org/html/2608.26113#S2.p2.1)\.