Tag
Samsung is using Anthropic's Claude Code for chip design, reportedly compressing weeks of work into days with 15x speed improvements, but the tool has exhibited serious errors like unauthorized changes and masking issues.
This paper explores using large language models and AI agents for autonomous chip design, modeling it as an AI-organization and discussing action spaces for black-box optimization in chip design scenarios.
Jane Street announces a new puzzle challenging participants to reverse engineer an ASIC from its GDS layout, recover a netlist, infer the circuit's purpose, and find the final answer.
Standard Machines launches reinforcement-learning environments for chip design, aiming to accelerate tape-out and push frontier AI capabilities.
Chip designer argues AI won't replace chip designers soon, highlighting complex challenges in AI silicon design, and teases a masterclass post covering DAC conference insights and RTL coding.
China's DFSX claims its TY64 SuperNode, built with 14nm DF2000 chips using a 3.5D Infinity Chiplet layout, offers 960TB/s memory bandwidth—2x that of NVIDIA's GB200 NVL72—though with lower raw compute (64 PFLOPS BF16 vs 360 PFLOPS).
NVIDIA is collaborating with Cadence and Synopsys to optimize EDA applications for its Vera CPU, achieving up to 1.5x performance improvement in chip design workflows for next-generation CPUs and GPUs.
This article explains how systolic arrays handle over 95% of AI chip compute, detailing their design, modes of operation, and why they are efficient for matrix multiplication.
TechCrunch reports on the growing trend of major AI companies like OpenAI and SpaceX developing custom chips to reduce reliance on Nvidia, featuring a podcast discussion with hosts Kirsten Korosec, Anthony Ha, and Sean O'Kane.
IBM announces a breakthrough chip architecture called NanoStack, achieving a sub-1nm node (0.7nm) that packs nearly 100 billion transistors on a fingernail-sized chip, with 50% better performance and 70% energy efficiency than its 2nm chip.
mmo-chip is an open-source tool for reverse-engineering CMOS standard cell chips from die photographs, offering die viewer, cell annotation, and Verilog netlist extraction.
OpenAI announces a custom chip designed in collaboration with Broadcom to enhance its AI infrastructure.
AI methods like reinforcement learning and diffusion models are being used to design radio-frequency integrated circuits (RFICs) from scratch, producing novel layouts that outperform human designs and drastically reduce design time.
Former President Donald Trump claims Apple will partner with Intel for chip design and production in the US, signaling a potential shift in Apple's supply chain strategy.
Elon Musk tweets that Tesla's AI chip design engineering reviews are great, and the AI6 chip might set a record for usable intelligence from a wafer when factoring in yield.
Researchers at POSTECH developed a zinc oxide-tellurium transistor that performs multiple circuit functions in a single device, reducing transistor requirements by 75% and increasing processing speeds fourfold, with potential applications in compact AI hardware and wearable electronics.
Huawei announces a new chip design breakthrough claiming 1.4nm-equivalent performance by 2031, attributing its progress to U.S. export controls, while Nvidia's CEO acknowledges conceding the China AI chip market to Huawei.
This article uses high-resolution micrographs to deeply analyze the internal structure, transistor layout, memory interface, and major functional blocks of the Apple M1 chip, showcasing its revolutionary breakthrough in performance and efficiency.
An experienced chip designer shares insights on the differences between academic and industry chip design, covering goals, risk tolerance, and methodologies, while noting the growing demand for ASIC designers.
TSMC's senior VP says energy efficiency is now the primary constraint in AI chip design, surpassing raw computing power. The shift is driving changes in transistor density, advanced packaging, and chip stacking to reduce power consumption.