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ByteDance is developing custom CPUs using Arm and RISC-V architectures to support its AI infrastructure and reduce reliance on Intel and AMD due to long processor delivery times.
Huawei discusses LogicFolding, a technique that compresses propagation time between adjacent flip-flops in circuit design, tightening critical paths and enabling faster chips. The company expects its high-end chips to achieve transistor density equivalent to 14 Å (1.4 nm) processes by 2031.
Google DeepMind chip engineer Reiner Pope delivers a comprehensive whiteboard explanation of how chips work, covering logic gates to systolic arrays and the human brain, in a free YouTube video.
The co-founder of Cerebras explains how their Wafer-Scale Engine (WSE) simplifies design compared to traditional NVIDIA GPUs.
Proposes MacroDiff+, a physics-guided geometric diffusion framework for macro placement in VLSI design, achieving 6.1–6.2% wirelength reduction on ISPD2005 benchmarks with superior stability and scalability.
Rule2DRC introduces a large-scale benchmark for DRC script synthesis with 1,000 tasks and 13,921 evaluation layouts, and proposes SplitTester, which uses execution feedback to improve program selection and functional correctness.
OpenAI and Broadcom announced a multi-year strategic collaboration to co-develop and deploy 10 gigawatts of custom AI accelerators and networking systems, with deployment beginning in mid-2026 and completion by end of 2029. This partnership enables OpenAI to design accelerators that embed learnings from frontier model development directly into hardware.
A detailed reverse-engineering analysis of the Intel 386 processor's I/O circuitry, explaining how it handles static electricity, latchup, and metastability to protect the chip.