@Huawei: What is LogicFolding? For circuit design, it aggressively compresses propagation time between adjacent flip-flops, tigh…
Summary
Huawei discusses LogicFolding, a technique that compresses propagation time between adjacent flip-flops in circuit design, tightening critical paths and enabling faster chips. The company expects its high-end chips to achieve transistor density equivalent to 14 Å (1.4 nm) processes by 2031.
View Cached Full Text
Cached at: 05/27/26, 01:16 AM
What is LogicFolding? For circuit design, it aggressively compresses propagation time between adjacent flip-flops, tightens critical path & enables chips to run faster. HUAWEI high-end chips are expected to feature transistor density equivalent to 14 Å (1.4 nm) processes by 2031. https://t.co/IfFpmrYNC8
Similar Articles
A new way to build chips: Sequentially stacking silicon to extend Moore's Law
Researchers at the University of Illinois have demonstrated a scalable method to sequentially stack high-performance silicon circuits, achieving monolithic 3D integration within strict thermal budgets, which could extend Moore's Law beyond traditional transistor shrinking.
Another ‘DeepSeek moment’? Huawei milestone alters China trajectory in chip race: analysts.
Huawei unveils the Tau Scaling Law, a chip architectural workaround to bypass US sanctions and achieve 1.4nm-equivalent transistor density by 2031, marking a significant step toward China's semiconductor self-sufficiency and altering the tech rivalry with Washington.
IBM has unveiled chip technology that could help extend Moore’s Law another decade
IBM has unveiled a new chip architecture called nanostack that vertically stacks transistors in two layers, enabling twice the transistor density of its previous technology. This breakthrough could extend Moore's Law for another decade and improve chip performance by 50% and energy efficiency by 70%.
@yashetal: Growing Boolean circuits never looked cool but now it is
Alex Mordvintsev introduces MorphoHDL, a minimal language prototype for growing boolean circuits using size-agnostic graph rewrite rules.
Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm
Samsung demonstrates the first 3D Stacked FETs with triple nanosheet channels at a 42nm gate pitch, presented at the 2026 VLSI Symposium, achieving a high review score and highlighting a new vertical transistor architecture for advanced logic scaling.