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SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration

arXiv cs.LG · 2026-06-11 Cached

SwiftCTS is a physics-informed surrogate framework that uses gradient-boosted ensembles and few-shot calibration to rapidly predict and Pareto-optimize clock tree metrics (power, wirelength, timing skew) across unseen designs, achieving high accuracy with minimal training data.

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Alpha-RTL: Test-Time Training for RTL Hardware Optimization

arXiv cs.LG · 2026-06-05 Cached

Alpha-RTL (TTT-RTL) introduces a test-time training framework for RTL hardware optimization, using reinforcement learning with EDA feedback to refine LLM-generated designs. It achieves significant PPA reductions on benchmarks.

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RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision

arXiv cs.AI · 2026-05-18 Cached

RTL-BenchMT is an agentic framework that automatically identifies and revises flawed cases and detects overfitting in RTL generation benchmarks, reducing human maintenance effort in EDA research.

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@dair_ai: NEW paper from NVIDIA. EDA tools like ABC have been hand-tuned by humans for decades. New research from NVIDIA shows th…

X AI KOLs Following · 2026-04-20 Cached

NVIDIA researchers present the first self-evolving logic synthesis framework where multi-agent LLMs autonomously refine the ABC EDA tool codebase.

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