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ESP32 Bit Pirate is an open-source hardware debugging ecosystem for ESP32-S3 boards, providing firmware, browser-based tools, and documentation for multi-protocol hardware hacking and development.
This article explains how to bring up the Linux kernel on a new platform, using an emulated RISC-V CPU as an example, with step-by-step guidance and code implementation for setting up minimal hardware components.
This blog post compares the performance and ease of use of Embassy (async Rust) against FreeRTOS (C) on an STM32F446 microcontroller, focusing on interrupt latency, memory usage, and programming simplicity.
TinyGo 0.42 introduces recoverable panics, Go 1.27 support, UEFI targets, and expanded hardware support for ESP32 and STM32, enhancing its capabilities for embedded systems development.
The article explains why boards using the same RK3588 chip can have different experiences, attributing it to secondary design factors like PCB routing, power supply, memory selection, interface exposure, and firmware maintenance by manufacturers.
The article describes the process of finding and fixing a bug in Go's netpoll mechanism that causes intermittent crashes on 32-bit embedded Linux systems, based on an unresolved issue in the Go project.
A personal blog post detailing the author's experience with cache coherence issues on a Terasic DE0-Nano-SOC board featuring Cortex-A9 processors, including hardware setup and debugging steps.
Espressif has released a Linux Board Support Package for the ESP32-S31 RISC-V based boards, enabling Linux development on this platform.
A developer uses Claude and other AI models to build a custom watch face for the PineTime smart watch, leveraging open-source firmware and simulators for an AI-assisted hacking project.
This article explains how to use Docker and Docker sandboxes for reproducible ESP32 firmware development, including integration with AI coding agents for safe, parallel environments.
David Chisnall presents CHERI, a hardware capability architecture enabling memory safety and fine-grained compartmentalization through ISA extensions such as ARM Morello, RISC-V, and CHERIoT microcontrollers. The talk emphasizes the importance of practical programming models for secure isolation.
Chiplab is a product that lets you test firmware on a virtual chip without needing physical hardware.
A maker describes building a portable 'anti AI computer' using Raspberry Pi Picos, a floppy drive, and a chorded keyboard, while reflecting on the irony that all the code was generated with AI.
This technical note from 1994 describes methods for constructing deterministic and nondeterministic finite state automata in Forth, emphasizing a one-to-one mapping between definitions and state tables to avoid slow nested IFs.
This paper evaluates Kolmogorov–Arnold Networks (KANs) versus MLPs as residual branches in hard-constrained recurrent physics-informed networks on an embedded RISC-V platform, finding KANs run slower, consume more energy, and are less dependable under INT8 quantization.
SCI Semiconductor announces the first silicon implementation of CHERIoT, a RISC-V-based security architecture providing deterministic memory safety and compartmentalization. The ICENI chip runs at up to 250 MHz and will be demonstrated at Embedded World.
NVIDIA showcases the Jetson platform for edge AI and robotics, highlighting the compact yet powerful Jetson Orin Nano Super developer kit that enables building AI agents and robots anywhere.
A practical guide to recursive filters (SMA, EMA, low-pass, and a tiny 1D Kalman) for smoothing noisy measurements with low latency and compute.
This paper proposes lightweight convolutional neural networks for detecting FPV drones using time-domain rasterized RF signals, eliminating frequency-domain preprocessing and achieving high accuracy with low computational cost, suitable for embedded systems.
This study explores the feasibility of classifying ten hand gestures using a single-channel sEMG signal combined with lightweight machine learning models, achieving up to 90% accuracy. It demonstrates potential for cost-effective, low-power gesture recognition.