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This repository provides source code for a RISC-V emulator and a tutorial to build a minimal Linux system from scratch, including device emulation and WebAssembly support.
Afonso Oliveira reports that Omarchy is running on RISC-V architecture with the SpacemiT K3 chip, using an out-of-tree kernel, and aims to develop further on open hardware.
This article explains how to bring up the Linux kernel on a new platform, using an emulated RISC-V CPU as an example, with step-by-step guidance and code implementation for setting up minimal hardware components.
An update to a RISC-V interpreter in Rust, featuring modularity, no_std support, compile-time execution, and strict specification compliance, utilizing many nightly Rust features.
SiFive has launched its first server platform, the BigSky SF-2U870, featuring 32 RISC-V cores, DDR5 memory, and PCIe 5.0 support, marking a significant step for RISC-V in high-performance computing.
CPython has officially added support for RISC-V architecture as a tier 3 platform, enabling Python to run on open-source instruction set hardware.
At Hot Chips 2026, Nvidia announced plans to extend CUDA support to RISC-V CPUs, outlining specific hardware requirements like server-grade CPUs, ACPI, and PCIe coherency to enable efficient GPU compute.
Espressif has released a Linux Board Support Package for the ESP32-S31 RISC-V based boards, enabling Linux development on this platform.
egos-2000 is a teaching operating system project that implements core operating system components in just 2000 lines of code. It features a clear three-layer architecture, supports the RISC-V platform, and comes with a textbook providing 9 course projects for convenient learning and practice.
Alibaba's XuanTie C950 RISC-V chip, fabricated by TSMC, now runs the Qwen-3.8 27B AI model natively at 30 tps, demonstrating vertical integration and enabling efficient edge AI deployment.
An embedded engineer from a third-world country responds to the article 'RISC-V: They Should Have Known Better', offering insights on RISC-V architecture and its implications.
A small experiment comparing the RISC-V RVA23 and ARMv9 computer architectures.
Dmitry.GR criticizes RISC-V's design, arguing it is not optimal for all use cases, especially microcontrollers, due to issues with code density and interrupt latency.
David Chisnall presents CHERI, a hardware capability architecture enabling memory safety and fine-grained compartmentalization through ISA extensions such as ARM Morello, RISC-V, and CHERIoT microcontrollers. The talk emphasizes the importance of practical programming models for secure isolation.
An interview with Fiora5 CEO Darian Domocos explores the challenges of building a RISC-V CPU IP startup, the role of open-source instruction sets, and how European chip sovereignty efforts create opportunities.
MiCoPro presents an end-to-end hardware/software co-design framework for mixed-precision quantization, using a hardware-aware proxy model to search optimal layer-wise bitwidths under latency constraints and deploy directly to edge hardware, achieving up to 40% latency reduction with less than 3% accuracy drop.
Comu is a compact 13×9.4mm development board built on the WCH CH32V203 RISC-V MCU that fits entirely inside a USB-A port, offering capacitive touch, LEDs, GPIO, and USB HID/serial/mass-storage capabilities. It is open-source and supports development via ch32fun, Rust, Arduino, and WCH tools.
This paper evaluates Kolmogorov–Arnold Networks (KANs) versus MLPs as residual branches in hard-constrained recurrent physics-informed networks on an embedded RISC-V platform, finding KANs run slower, consume more energy, and are less dependable under INT8 quantization.
The Dabao evaluation board features the Baochip-1x, an open-source, NDA-free SoC with hardware security features and a 700 MHz quad-core RISC-V I/O coprocessor, targeting embedded developers and hobbyists.
SCI Semiconductor announces the first silicon implementation of CHERIoT, a RISC-V-based security architecture providing deterministic memory safety and compartmentalization. The ICENI chip runs at up to 250 MHz and will be demonstrated at Embedded World.