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该论文首次提出基于多目标强化学习的 LLM RTL 电路生成方法，通过 Hypervolume Contribution 奖励优化整组电路的 PPA 权衡多样性，在 RTLLM v2 基准上较单目标 RL 基线提升 14.4 个百分点的相对超体积。
VeriTrace, a multi-agent system for automated Verilog RTL generation, introduces Agentic Temporal Exploration that gives debugging agents full control over signal selection, time windows, and iteration depth, achieving 100% Pass@1 on VerilogEval-V2 and outperforming baselines by +5.1%.
RTL-BenchMT is an agentic framework that automatically identifies and revises flawed cases and detects overfitting in RTL generation benchmarks, reducing human maintenance effort in EDA research.