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TSMC presents A14 NanoFlex Pro platform at IEDM with record SRAM density and PPA improvements over N2 technology, on track for volume production in 2028.
A technical deep-dive explaining what a memory compiler is, how it uses bitcells to generate SRAM layouts, and the design concepts involved from cross-coupled inverters to GDS tiling.
A thread analyzing how six AI chip competitors (Tenstorrent, Cerebras, Trainium, TPU, SambaNova, Furiosa) all independently abandoned traditional GPU features like hardware caches and threads, using software-managed SRAM and different programming models, contrasting with NVIDIA's CUDA approach.