transistor

Samsung demonstrates the first 3D Stacked FETs with triple nanosheet channels at a 42nm gate pitch, presented at the 2026 VLSI Symposium, achieving a high review score and highlighting a new vertical transistor architecture for advanced logic scaling.

Researchers at POSTECH developed a zinc oxide-tellurium transistor that performs multiple circuit functions in a single device, reducing transistor requirements by 75% and increasing processing speeds fourfold, with potential applications in compact AI hardware and wearable electronics.