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OpenRTLSet introduces the largest fully open-source dataset for hardware design with over 131,000 Verilog code samples, enabling fine-tuning of LLMs for Verilog code generation.
An open source silicon reverse engineering tool, MMO-CHIP, enables rapid annotation and Verilog generation from microscope images of custom chips, reducing the process from weeks to under an hour.
StepPRM-RTL is a novel framework combining stepwise trajectory modeling, process-reward modeling (PRM), and retrieval-augmented fine-tuning (RAFT) to improve LLM-based RTL code generation for Verilog and VHDL, outperforming prior methods by over 10% in functional correctness metrics.
Verilog-Evolve is a feedback-driven framework that iteratively refines Verilog code generated by large language models, using functional simulation, synthesis, and timing metrics to promote better candidates and evolve reusable repair skills across tasks.
The article draws parallels between the security flaws in C/C++ and those in Verilog, arguing that the hardware description language's design leads to bugs and that the industry should invest in safer alternatives, similar to the push for memory-safe programming languages in software.
This article describes the CRC Generator, a command-line tool for generating Verilog/VHDL CRC code, and its archival on GitHub by Julia Desmazes to preserve the tool originally by Evgeni Stavinov.
CPPL is a compiler-mediated framework that bridges LLMs and hardware design by using a Python DSL and JSON-based intermediate representation to enable statically checkable, optimizable RTL generation.
A detailed blog series documenting the design and implementation of a scientific calculator from scratch using FPGA, covering numerical methods, CPU architecture, microcode, and hardware prototyping.
This project implements a fully functional scientific calculator in hardware using an FPGA, including a custom soft CPU, microcode firmware, and supporting tools. It provides a web-based simulator and open-source Verilog code.