From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis

# From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis
Source: [https://arxiv.org/html/2610.38201](https://arxiv.org/html/2610.38201)
Huan ChenJiahua YingRan OuWeilong ChenLi XueKai Sun††thanks:Corresponding AuthorAffiliation:State Key Laboratory of Power System Operation and ControlAffiliation:Department of Electrical EngineeringAffiliation:Tsinghua UniversityAffiliation:Beijing, ChinaAffiliation:subw24@mails\.tsinghua\.edu\.cn, sun\-kai@mail\.tsinghua\.edu\.cn

###### Abstract

Designing power electronics converters traditionally requires intensive human expertise across topology sizing, commercial component selection, circuit simulation verification, and schematic drafting\. While Large Language Models \(LLMs\) show promise in electronic design automation \(EDA\), applying standalone LLMs directly to board\-level power electronics schematic synthesis suffers from severe engineering hallucinations—including inaccurate analytical sizing, fabricated or mismatched component part numbers, violated voltage derating margins, and broken topological connectivity\. In this paper, we propose a Bounded Dual\-Loop Automated Schematic Synthesis Framework that translates natural language specifications into verified, editable KiCad schematics and manufacturing deliverables\. Our workflow integrates six stages across three functional columns: \(1\) requirement parsing and knowledge\-driven power stage synthesis covering non\-isolated \(Buck, Boost\) and isolated/resonant \(Flyback, DAB, half\-bridge LLC\) topologies; \(2\) contract\- and evidence\-coordinated component selection grounded in distributor APIs and OEM datasheets, coupled with closed\-loopngspicetransient verification and stress feedback; and \(3\) modular control hardware integration and multi\-format deliverable generation featuring native KiCad netlist round\-trip verification\. End\-to\-end case studies on a24​–​36​V24\\text\{\-\-\}36\\,\\text\{V\}to12​V/2​A12\\,\\text\{V\}/2\\,\\text\{A\}Buck converter \(29 positions, 83 verified terminals\) and an isolated48​V48\\,\\text\{V\}to24​V/0\.5​A24\\,\\text\{V\}/0\.5\\,\\text\{A\}Dual\-Active Bridge \(DAB\) converter \(87 positions, 341 verified terminals\), alongside comparative evaluations against a Vanilla LLM baseline, demonstrate that our framework improves component verification coverage from22\.2%22\.2\\%to98\.6%98\.6\\%, nominal value consistency from0\.0%0\.0\\%to97\.7%97\.7\\%, and SPICE simulation pass rates from0\.0%0\.0\\%to100\.0%100\.0\\%\.

*K*eywordsPower electronics⋅\\cdotLarge language models⋅\\cdotSchematic synthesis⋅\\cdotAgentic workflow⋅\\cdotSPICE\-in\-the\-loop⋅\\cdotElectronic design automation \(EDA\)

## 1Introduction

Power electronics serves as the foundational backbone of modern electrical energy conversion and management, playing a pivotal role in renewable energy integration, electric vehicles \(EVs\), industrial motor drives, and next\-generation artificial intelligence \(AI\) data center power delivery networks, as shown in Figure 1\. With the rapid proliferation of wide\-bandgap \(WBG\) semiconductors—such as Silicon Carbide \(SiC\) and Gallium Nitride \(GaN\)—and increasingly diverse application scenarios, the industry faces an urgent demand for customized power converters spanning a wide range of voltage and power ratings\. Accelerating the hardware development lifecycle and achieving rapid prototyping from high\-level system specifications have become critical competitive advantages in modern power electronics engineering\.

Within the power electronics development lifecycle, circuit schematic design stands as the most critical link bridging abstract functional requirements and physical hardware implementation\. A complete engineering schematic not only defines the circuit topology and connectivity but also dictates specific commercial component selections, electrical and thermal stress margins, and downstream printed circuit board \(PCB\) layout constraints\. Traditionally, translating a functional requirement \(e\.g\., converting a 500V DC bus to a regulated 200V output\) into a production\-ready schematic is a labor\-intensive, iterative process heavily reliant on experienced human engineers\. Engineers must manually select appropriate topologies, derive steady\-state and dynamic equations to size passive components, comb through massive distributor catalogs and datasheets to select discrete semiconductors, construct simulation models to verify waveforms, and finally compile engineering deliverables such as the Bill of Materials \(BOM\) and netlists\. This high barrier to entry and prolonged iteration cycle severely bottleneck design productivity\.

![Refer to caption](https://arxiv.org/html/2610.38201v1/figure/figure1.png)Figure 1:Application scenarios of power electronicsWhile early electronic design automation \(EDA\) efforts in power electronics introduced expert systems and metaheuristic optimization algorithms \(e\.g\., genetic algorithms and particle swarm optimization\) to assist in parameter sizing, these rigid frameworks require predefined mathematical formulations for fixed topologies and lack the flexibility to process natural language intent or generate comprehensive engineering documentation\. Recently, Large Language Models \(LLMs\) have demonstrated remarkable capabilities in software engineering and digital integrated circuit design \(such as automated Verilog generation\)\. However, directly applying a standalone, monolithic LLM to power electronics schematic design encounters severe practical bottlenecks:

1. 1\.Inaccurate Analytical Computation:As probabilistic token predictors, standalone LLMs frequently fail at precise numerical calculations required for power stage sizing \(e\.g\., inductance, capacitance, and root\-mean\-square current derivations\), leading to physically mismatched circuit parameters\.
2. 2\.Component Hallucination and Lack of Engineering Experience:Vanilla LLMs lack real\-time access to commercial supply chains and practical engineering heuristics\. Consequently, they often fabricate non\-existent part numbers or neglect critical safety derating rules \(e\.g\., selecting a 500V\-rated MOSFET for a 500V bus without accounting for switching voltage spikes\), which would result in immediate catastrophic failure in real hardware\.
3. 3\.Open\-Loop Generation without Physical Verification:Generating a circuit schematic or netlist in a single pass without circuit simulator feedback provides no guarantee of electrical functionality, often yielding syntax\-broken netlists, non\-convergent simulations, or severe deviations in steady\-state output voltage and ripple specifications\.

To overcome these challenges, we propose an automated, end\-to\-end agentic workflow that synthesizes verified power electronics schematics and complete engineering deliverables directly from natural language prompts \(e\.g\.,“Design a 500V\-to\-200V Buck converter”\)\. Rather than relying on a single LLM’s internal parametric memory, our framework orchestrates the LLM with specialized external tools and domain\-specific engineering rules\. Specifically, the workflow parses user requirements and invokes programmatic calculation modules embedded with practical engineering derating margins to derive exact theoretical component stresses\. Subsequently, it bridges the gap between theoretical specs and real\-world hardware by querying commercial electronic component distributor APIs to select authentic, in\-stock devices\. Furthermore, to ensure electrical reliability, the workflow constructs an executable SPICE netlist and establishes a closed\-loop verification mechanism with NGSPICE\. By automatically analyzing simulated time\-domain waveforms against design targets, the agent iteratively refines circuit parameters until full functional compliance is achieved, ultimately outputting the finalized schematic, BOM, netlist, and design documentation\.

The primary contributions of this paper are summarized as follows:

- •An End\-to\-End Schematic Synthesis Workflow:We develop a novel LLM\-based agentic architecture tailored for power electronics engineering, automating the entire pipeline from natural language requirement parsing to the generation of complete schematics, BOMs, SPICE netlists, and design specifications\.
- •API\-Grounded Component Selection with Engineering Heuristics:We eliminate LLM component hallucinations by integrating real\-world distributor APIs with domain\-specific voltage/current derating rules, ensuring that all synthesized schematics utilize commercially available and safely rated power devices\.
- •Closed\-Loop NGSPICE Verification:We introduce a simulation\-in\-the\-loop self\-correction mechanism that validates generated circuits via NGSPICE transient simulations, enabling automated diagnosis and iterative tuning of circuit parameters to guarantee steady\-state and ripple performance\.

The remainder of this paper is organized as follows\. Section[2](https://arxiv.org/html/2610.38201#S2)reviews related work in automated power electronics design and LLM\-aided hardware synthesis\. Section[3](https://arxiv.org/html/2610.38201#S3)details the system architecture and the four core stages of the proposed automated workflow\. Section[4](https://arxiv.org/html/2610.38201#S4)presents an end\-to\-end engineering case study on a 500V\-to\-200V converter alongside ablation evaluations\. Section[5](https://arxiv.org/html/2610.38201#S5)discusses current limitations and future extensions, and Section[6](https://arxiv.org/html/2610.38201#S6)concludes the paper\.

## 2Related Work

### 2\.1Design Automation and AI in Power Electronics

Automating the design of power electronics converters has been a long\-standing pursuit to reduce engineering development cycles and optimize system performance\[[1](https://arxiv.org/html/2610.38201#bib.bib2)\]\. As comprehensively reviewed by Zhao et al\.\[[2](https://arxiv.org/html/2610.38201#bib.bib1)\], traditional artificial intelligence \(AI\) and computer\-aided design \(CAD\) techniques in power electronics have primarily relied on expert systems, metaheuristic algorithms \(e\.g\. genetic algorithms and particle swarm optimization\), and data\-driven surrogate models to optimize converter efficiency, weight, or thermal performance\[[3](https://arxiv.org/html/2610.38201#bib.bib4)\]\. In terms of physical and module\-level automation, tools such as PowerSynth\[[4](https://arxiv.org/html/2610.38201#bib.bib3)\]have pioneered layout synthesis and electro\-thermal optimization for multichip power modules\.

Recently, inspired by the reasoning capabilities of foundation models, researchers have begun exploring Large Language Models \(LLMs\) for power electronics applications\. Notably, Lin et al\. proposed PE\-GPT\[[5](https://arxiv.org/html/2610.38201#bib.bib5)\], a multimodal LLM framework enhanced with retrieval\-augmented generation \(RAG\) and metaheuristic algorithms to assist in dual\-active bridge \(DAB\) modulation design and converter parameter sizing\. Similarly, Guo et al\.\[[6](https://arxiv.org/html/2610.38201#bib.bib6)\]demonstrated a customized GPT framework for photovoltaic boost converter design and verification\. However, these pioneering efforts primarily focus on theoretical parameter optimization or modulation strategy selection\. They do not address the automated synthesis of complete engineering schematics grounded in real\-time commercial component supply chains, nor do they automate the generation of manufacturing deliverables such as BOMs and verified netlists\.

### 2\.2Large Language Models for Hardware and Circuit EDA

In the broader Electronic Design Automation \(EDA\) community, LLMs have catalyzed a paradigm shift in hardware synthesis\[[7](https://arxiv.org/html/2610.38201#bib.bib14)\]\. Initially, research efforts concentrated on digital integrated circuit \(IC\) design, leveraging domain\-adapted LLMs to generate Register\-Transfer Level \(RTL\) Verilog code and EDA tool scripts, exemplified by NVIDIA’s ChipNeMo\[[8](https://arxiv.org/html/2610.38201#bib.bib7)\]and VerilogEval\[[9](https://arxiv.org/html/2610.38201#bib.bib8)\]\.

More recently, attention has expanded from digital logic to analog circuit topology generation and SPICE netlist synthesis\. For instance, AnalogCoder\[[10](https://arxiv.org/html/2610.38201#bib.bib9)\]introduced a training\-free LLM agent that generates Python\-based PySpice code to design analog amplifiers via feedback\-driven prompts\. Similarly, SPICEPilot\[[11](https://arxiv.org/html/2610.38201#bib.bib10)\]and AnalogXpert\[[12](https://arxiv.org/html/2610.38201#bib.bib11)\]explored LLM\-guided SPICE code generation and subcircuit\-level topology synthesis\. Despite these advances, existing circuit\-level LLM frameworks target low\-voltage, integrated CMOS analog circuits, where design degrees of freedom are largely confined to transistor channel width\-to\-length \(W/LW/L\) sizing\. In contrast, board\-level power electronics schematic design operates under high\-voltage and high\-current switching regimes\. It requires selecting discrete commercial off\-the\-shelf \(COTS\) power semiconductors \(e\.g\., SiC MOSFETs, fast\-recovery diodes\) and passive components with strict voltage/current derating margins—a critical engineering dimension absent in IC\-oriented LLM frameworks\.

### 2\.3Tool\-Augmented and Verification\-in\-the\-Loop Agents

To mitigate the inherent limitations of standalone LLMs in mathematical calculation and factual accuracy, the AI community has developed agentic paradigms that interleave reasoning with external tool execution, such as ReAct\[[13](https://arxiv.org/html/2610.38201#bib.bib12)\]and Toolformer\[[14](https://arxiv.org/html/2610.38201#bib.bib13)\]\. By delegating arithmetic operations to symbolic interpreters and querying external APIs, tool\-augmented agents significantly curb hallucinations\. Furthermore, incorporating domain\-specific verifiers \(such as compilers or physical simulators\) into an iterative self\-correction loop has proven essential for reliable engineering synthesis\[[10](https://arxiv.org/html/2610.38201#bib.bib9)\]\. Building upon these agentic principles, our work establishes a specialized closed\-loop workflow for power electronics: we bridge theoretical analytical sizing with commercial distributor APIs for authentic component selection, and close the verification loop via automated NGSPICE transient simulations to guarantee functional schematic synthesis\.

## 3Proposed Automated Synthesis Workflow

![Refer to caption](https://arxiv.org/html/2610.38201v1/figure/figure2.png)Figure 2:The proposedBounded Dual\-Loop Automated Schematic Synthesis Framework\. The architecture is organized into three functional columns from left to right: \(1\)Input Specifications, \(2\)Iteration & Search Engine, and \(3\)Integration & Deliverables\. Deep purple solid arrows denote the forward synthesis and integration pipeline, whereas coral\-orange solid arrows highlight the diagnostic feedback pathways \(Refine Query,Re\-design,Stress Feedback, andResize L/C\) governed by Decision Nodes 1 and 2\.To translate unstructured natural language design requests into physically valid, manufacturing\-ready power electronics hardware, we formulate the schematic design process as a knowledge\-constrained, bounded dual\-loop workflow\. Rather than relying on open\-loop text generation, our framework coordinates symbolic domain knowledge, multi\-source commercial supply\-chain evidence, and time\-domain circuit simulation\.

### 3\.1System Overview and Bounded Dual\-Loop Architecture

As illustrated in Figure[2](https://arxiv.org/html/2610.38201#S3.F2), the overallBounded Dual\-Loop Automated Schematic Synthesis Frameworkis structured horizontally across three functional columns encompassing six interconnected stages:

1. 1\.Column 1 – Input Specifications:EncompassesStage 1 \(Parsing & Constraint Modeling\)andStage 2 \(Knowledge\-Driven Synthesis\), bridging natural language requirements, modular topology knowledge blocks, and engineering derating priors into a parameterized power graph𝒢pwr\\mathcal\{G\}\_\{\\text\{pwr\}\}\.
2. 2\.Column 2 – Iteration & Search Engine:EncompassesStage 3 \(Real Component Selection\)andStage 4 \(Power\-Stage SPICE Verification\), executing contract\-based device retrieval and automated NGSPICE verification governed by two diagnostic decision nodes\.
3. 3\.Column 3 – Integration & Deliverables:EncompassesStage 5 \(Modular Control Integration\)andStage 6 \(Deliverables & Consistency Check\), assembling peripheral control hardware and compiling multi\-format deliverables via a Shared Structured Circuit Intermediate Representation \(IR\)\.

In Figure[2](https://arxiv.org/html/2610.38201#S3.F2), the primary forward progression is indicated bydeep purple solid arrows, while diagnostic self\-correction pathways are depicted bycoral\-orange solid arrows\. Crucially, Column 2 operates as a“Design–Selection–Simulation–Feedback” bounded closed loopgoverned by two diagnostic decision nodes:

- •Inner Loop \(Decision 1: Selection Adequate?\):Audits whether every physical component position in the synthesized topology is assigned a specific commercial part number backed by verified datasheet/distributor evidence and compliant electrical ratings\. When unmet, the coral\-orange feedback pathways either route back to Stage 3 \(Refine Query\) to expand candidate retrieval and evidence parsing, or escalate across the column boundary back to Stage 2 \(Re\-design\) if physical COTS devices cannot satisfy the theoretical parameters\. Upon passing \(Yes \(Pass\)\), execution proceeds to Stage 4\.
- •Outer Loop \(Decision 2: Targets & Stress Verified?\):Audits whether the compiled circuit executes properly in NGSPICE and satisfies declared steady\-state, ripple, and gate\-drive targets, while comparing extracted time\-domain electrical stresses against component contracts\. If simulated stresses exceed initial estimates, the outer loop routes back to Stage 3 via theStress Feedbackpathway to update selection contracts and re\-select higher\-rated parts; if output voltage or ripple targets fail, it routes back to Stage 2 via theResize L/Cpathway to retune passive or modulation parameters\. Once verified \(Pass\), the workflow advances to Column 3\.

##### Bounded Termination and Execution Scope\.

To guarantee deterministic engineering execution, user\-defined functional requirements and acceptance boundaries remain immutable throughout the loops, while feedback iteratively adjusts candidate pools, allowed design degrees of freedom, and model bindings\. The workflow terminates either when all verification targets are satisfied or when predefined computational, retrieval, and iteration budgets are exhausted—in which case the system outputs the best\-effort design alongside explicit unresolved items and diagnostic logs\. In our current implementation, the default basic execution path incorporates reference power\-stage simulation with a single\-pass stress\-feedback re\-selection, whereas a strict device\-model\-bound entry point supports multi\-iteration bounded repair loops\.

### 3\.2Input Specifications: Parsing and Knowledge\-Driven Synthesis

#### 3\.2\.1Stage 1: Parsing and Constraint Modeling

As shown at the top of Column 1 in Figure[2](https://arxiv.org/html/2610.38201#S3.F2), the workflow begins by establishing a formal interface between aNatural Language Requirement\(e\.g\.,“Design a 500V\-to\-200V Buck converter…”\) and electrical engineering constraints\. Combining the user prompt withModular Topology Knowledge Blocks, Stage 1 extracts key specification tuples—including topology family, input/output ratings \(Vin,Vout,PoutV\_\{\\text\{in\}\},V\_\{\\text\{out\}\},P\_\{\\text\{out\}\}\), switching frequencyfsf\_\{s\}, ripple tolerances, and isolation requirements\. The module performs automatic unit normalization, completeness checking, and consistency validation\. Importantly, the parser distinguishes between mandatory user constraints, engineering preferences, and unspecified conditions, outputting a formal specification set𝒞spec\\mathcal\{C\}\_\{\\text\{spec\}\}\.

#### 3\.2\.2Stage 2: Knowledge\-Driven Synthesis

Guided by𝒞spec\\mathcal\{C\}\_\{\\text\{spec\}\}and bottom\-upEngineering Derating Priors\(e\.g\., voltage and current safety margin curves\), Stage 2 synthesizes the power stage through three coordinated sub\-modules:

1. 1\.Analytical Sizing Engine:Computes key circuit parameters—such as duty cycleDD, filtering inductances and capacitances \(L,CL,C\), transformer turns ratios \(Np:NsN\_\{p\}:N\_\{s\}\), and resonant tank parameters \(Lr,CrL\_\{r\},C\_\{r\}\)—across five supported topologies: - •Buck and Boost:Passive components and duty cycles are sized via inductor volt\-second balance and capacitor ampere\-second balance under continuous conduction mode \(CCM\) ripple constraints: Lbuck=Vout​\(Vin−Vout\)Δ​IL⋅fs⋅Vin,Cout,buck=Δ​IL8⋅fs⋅Δ​VoutL\_\{\\text\{buck\}\}=\\frac\{V\_\{\\text\{out\}\}\(V\_\{\\text\{in\}\}\-V\_\{\\text\{out\}\}\)\}\{\\Delta I\_\{L\}\\cdot f\_\{s\}\\cdot V\_\{\\text\{in\}\}\},\\quad C\_\{\\text\{out,buck\}\}=\\frac\{\\Delta I\_\{L\}\}\{8\\cdot f\_\{s\}\\cdot\\Delta V\_\{\\text\{out\}\}\}\(1\) - •Flyback:Magnetizing inductanceLmL\_\{m\}, turns ratioNp:NsN\_\{p\}:N\_\{s\}, and operating points are determined from per\-cycle inductive energy storage, volt\-second demagnetization relations, and reflected voltage limits\. - •Dual\-Active Bridge \(DAB\):Based on single\-phase\-shift \(SPS\) power transfer, the series inductanceLsL\_\{s\}and reference phase\-shift ratioϕ\\phiare synthesized via: PDAB=n​Vin​Vout2​fs​Ls​ϕ​\(1−\|ϕ\|\)P\_\{\\text\{DAB\}\}=\\frac\{nV\_\{\\text\{in\}\}V\_\{\\text\{out\}\}\}\{2f\_\{s\}L\_\{s\}\}\\phi\(1\-\|\\phi\|\)\(2\) - •Half\-Bridge LLC:Utilizing First Harmonic Approximation \(FHA\), resonant parameters \(Lr,Cr,LmL\_\{r\},C\_\{r\},L\_\{m\}\) are synthesized to ensure inductive\-region operation for Zero\-Voltage Switching \(ZVS\)\.
2. 2\.Coupled Magnetic Configuration:For transformer\-isolated topologies \(Flyback, DAB, LLC\), literature\-backed winding configurations and physical core rules are incorporated so that realistic magnetic parameters directly participate in circuit synthesis\.
3. 3\.Parameterized Power Graph \(𝒢pwr\\mathcal\{G\}\_\{\\text\{pwr\}\}\):Aggregates the synthesized topology connectivity, gate\-driver interface requirements, and an executable verification test plan, forwarding them to Column 2\.

### 3\.3Iteration and Search Engine: Selection and SPICE Verification

#### 3\.3\.1Stage 3: Real Component Selection

Entering Column 2 of Figure[2](https://arxiv.org/html/2610.38201#S3.F2), the requirements embedded in𝒢pwr\\mathcal\{G\}\_\{\\text\{pwr\}\}are formalized into position\-specificSelection Contracts \(𝒦i\\mathcal\{K\}\_\{i\}\), defining nominal value bounds, voltage/current/power ratings, supply voltages, and interface rules\. Stage 3 executes three sequential steps:

1. 1\.Multi\-Source Candidate Pool:Generates parametric search queries to retrieve candidate parts from local curated catalogs, the real\-timeMouser API, and OEM datasheets\.
2. 2\.Evidence Verification & LLM Parsing:Performs identity association, unit normalization, and provenance auditing\. For unstructured datasheet text requiring semantic interpretation, the LLM proposes interpretations that are strictly cross\-checked against original document excerpts and deterministic rules\.
3. 3\.Contract Matching Engine:Evaluates normalized candidates item\-by\-item against𝒦i\\mathcal\{K\}\_\{i\}while accounting for package type, thermal limits, operating frequency, and parameter guarantee types\.

As summarized in the upper half of Table[1](https://arxiv.org/html/2610.38201#S3.T1),Decision 1governs the inner loop: if selection is inadequate, the system invokes either theRefine Querypathway back to Stage 3 or theRe\-designpathway back to Stage 2\.

Table 1:Diagnostic Routing Logic and Solid Feedback Pathways at Decision Nodes 1 and 2
#### 3\.3\.2Stage 4: Power\-Stage SPICE Verification

Once Decision 1 yieldsYes \(Pass\), Stage 4 compiles the circuit into an executable SPICE netlist and invokes anAutomated Testbench & NGSPICEengine \(supplying input sources, loads, auxiliary supplies, and gate\-drive modulation signals\) to run nominal and fine\-step transient simulations\. Next, theWaveform & Stress ExtractionandStress\-Feedback Auditmodules evaluate steady\-state output voltage, voltage/current ripples, and gate\-drive behavior, while extracting terminal peak voltages, peak currents, and RMS currents across all components\.

As detailed in the lower half of Table[1](https://arxiv.org/html/2610.38201#S3.T1),Decision 2governs the outer loop: electrical target violations trigger theResize L/Cpathway back to Stage 2, whereas elevated component stresses trigger theStress Feedbackpathway back to Stage 3 to update𝒦i\\mathcal\{K\}\_\{i\}and re\-select affected devices\.

### 3\.4Integration and Deliverables: Control Hardware and Consistency Check

#### 3\.4\.1Stage 5: Modular Control Integration

Upon passing Decision 2 \(Pass\), execution transitions to Column 3 of Figure[2](https://arxiv.org/html/2610.38201#S3.F2)\. Stage 5 performsController IC Configuration\(supporting analog PWM, digital PWM, and integrated half\-bridge controllers\) and assembles standardizedPeripheral Application Modules—including supply decoupling, voltage references, timing networks, reset circuits, sensing interfaces, logic level shifting, and gate\-driver connections\. ThroughExplicit Scope Separation, Stage 5 focuses strictly on control hardware selection and pin\-level connectivity \(excluding control algorithm synthesis, DSP firmware, or closed\-loop stability design\) and stores the control hardware results separately from the verified power\-stage simulation model\.

#### 3\.4\.2Stage 6: Deliverables and Consistency Check

Both the verified power\-stage design and modular control hardware are unified into aShared Structured Circuit IR—a central graph linking topological nodes, verified MPNs, simulation models, and datasheet evidence\. From this unified IR, Stage 6 generates five synchronized engineering deliverables:

1. 1\.Engineering Design Report:Summarizing parsed requirements, analytical sizing derivations, selection evidence, and design boundaries\.
2. 2\.Production BOMand3\. SPICE Netlist:Providing verified MPNs, manufacturers, quantities, key ratings, and executable SPICE netlists\.
3. 4\.Simulation & Stress Report:Archiving operating conditions, measured metrics, voltage/current waveforms, stress profiles, and model hierarchy declarations\.
4. 5\.Editable KiCad Schematic \(\.kicad\_sch\):Generates an editable schematic file coupled with an automatedNative Netlist Read\-Back Verificationmodule, which exports the native netlist back from KiCad to verify 100% topological consistency against the Shared Structured Circuit IR\.

## 4Case Studies and Experimental Evaluation

To evaluate the effectiveness, topological generalizability, and engineering rigor of the proposed workflow, we first detail our system implementation, then present two comprehensive end\-to\-end synthesis case studies—a non\-isolated Buck converter and an isolated Dual\-Active Bridge \(DAB\) converter—and finally conduct a quantitative and diagnostic comparison against a one\-shot Vanilla LLM baseline\.

### 4\.1Implementation Details

The proposed framework is implemented in modular Python, orchestrating requirement compilation, topology knowledge synthesis, evidence\-backed component selection, SPICE simulation verification, and multi\-format deliverable generation\. All experiments were executed locally on a 64\-bit Windows 10 workstation equipped with an Intel Core i7\-13700F CPU \(16 cores, 24 threads\) and 32 GB of RAM\. The primary workflow engine runs under Python 3\.14\.5 \(with NumPy 2\.4\.6 and Matplotlib 3\.10\.9 for waveform post\-processing\), while a dedicated Python 3\.12\.14 runtime handles PDF datasheet parsing and page rendering viapdfplumberandpypdfium2\. Time\-domain circuit simulations are solved usingngspice 47, and editable schematics along with native netlist round\-trip checks are generated viaKiCad CLI 10\.0\.0\.

Table 2:Summary of Core Implementation and Experimental SettingsTable[2](https://arxiv.org/html/2610.38201#S4.T2)summarizes the key system configurations\. In our default power\-stage execution path \(language\_spice / power\_stage / basic\), requirement parsing, topology equations, and baseline contract matching are executed deterministically, followed by externally modulated power\-stage and gate\-driver simulation inngspice 47with one bounded stress\-feedback re\-selection pass\. For semantic datasheet extraction tasks, the system invokesqwen3\.5\-plus\-2026\-04\-20via a hosted Chat Completions endpoint \(client\-side sampling parameters such as temperature and top\-ppare left unspecified at their server defaults\)\. LLM outputs are treated strictly as candidate proposals that must pass deterministic provenance and document grounding checks against source PDFs before adoption\. Importantly, reference power\-stage simulation models, commercial BOM realizations, and modular controller\-hardware proposals are logged separately to maintain transparent verification boundaries\.

### 4\.2End\-to\-End Case Study I: Non\-Isolated Buck Converter

##### Design Task and Knowledge\-Driven Synthesis\.

The first case study evaluates a non\-isolated step\-down converter triggered by the natural language prompt:“Buck input 24\-36V output 12V 2A 80kHz non\-isolated ripple 5%”\. The requirement parser normalizes the specifications intoVin∈\[24,36\]​VV\_\{\\text\{in\}\}\\in\[24,36\]\\,\\text\{V\},Vout=12​VV\_\{\\text\{out\}\}=12\\,\\text\{V\},Iout=2​AI\_\{\\text\{out\}\}=2\\,\\text\{A\}\(Pout=24​WP\_\{\\text\{out\}\}=24\\,\\text\{W\}\),fs=80​kHzf\_\{s\}=80\\,\\text\{kHz\}, and a peak\-to\-peak output voltage ripple limit ofΔ​Vout,max=0\.6​Vpp\\Delta V\_\{\\text\{out,max\}\}=0\.6\\,\\text\{V\}\_\{\\text\{pp\}\}\(5%5\\%\)\. Invoking the Buck knowledge module under volt\-second balance and ripple constraints yields theoretical reference parameters ofLmain=166\.667​μ​HL\_\{\\text\{main\}\}=166\.667\\,\\mu\\text\{H\},Cout=151\.982​μ​FC\_\{\\text\{out\}\}=151\.982\\,\\mu\\text\{F\},Cin=30\.396​μ​FC\_\{\\text\{in\}\}=30\.396\\,\\mu\\text\{F\}, current\-sense resistorRCS=3\.846​m​ΩR\_\{\\text\{CS\}\}=3\.846\\,\\text\{m\}\\Omega, gate resistorRgate=10​ΩR\_\{\\text\{gate\}\}=10\\,\\Omega, and bootstrap capacitorCboot=1\.5​μ​FC\_\{\\text\{boot\}\}=1\.5\\,\\mu\\text\{F\}\.

Table 3:Synthesized Parameters and Selected Core Commercial Components for Case Study I \(Buck\) and Case Study II \(DAB\)Functional Role \(Designator\)Theoretical / Ref\.Selected NominalVerified Part Number \(Mfr\.\)QtyCase Study I: Non\-Isolated Buck Converter \(29 physical positions, 22 unique MPNs in total\)High\-Side Switch \(QSW / Q1\)Vin,max=36​VV\_\{\\text\{in,max\}\}=36\\,\\text\{V\}600​V,41​m​Ω600\\,\\text\{V\},41\\,\\text\{m\}\\OmegaIPW60R041P6FKSA1\(Infineon\)1Freewheeling Diode \(DFREE / D1\)Iout=2​AI\_\{\\text\{out\}\}=2\\,\\text\{A\}200​V,3​A200\\,\\text\{V\},3\\,\\text\{A\}UF3004\-HF\(Comchip\)1Main Inductor \(LMAIN / L1\)166\.67​μ​H166\.67\\,\\mu\\text\{H\}180​μ​H180\\,\\mu\\text\{H\}760800301\(Würth Elektronik\)1Output Capacitor \(COUT / C1\)151\.98​μ​F151\.98\\,\\mu\\text\{F\}150​μ​F150\\,\\mu\\text\{F\}\(200​V200\\,\\text\{V\}\)EKXJ201ELL151MJ50S\(Chemi\-Con\)1Input Capacitor \(CIN / C2\)30\.40​μ​F30\.40\\,\\mu\\text\{F\}30​μ​F30\\,\\mu\\text\{F\}\(600​V600\\,\\text\{V\}\)C44AHFP5300ZC0J\(KEMET\)1Sense Resistor \(RCS / R1\)3\.85​m​Ω3\.85\\,\\text\{m\}\\Omega3\.9​m​Ω3\.9\\,\\text\{m\}\\OmegaSL1TTE3L9J\(KOA Speer\)1Gate Driver \(GD\_main / U1\)High/Low\-SideHalf\-Bridge DriverUCC27714D\(Texas Instruments\)1Analog Controller \(CONTROL / U3\)Peripheral Mod\.Current\-Mode PWMUCC28C53DR\(Texas Instruments\)1Case Study II: Isolated Dual\-Active Bridge \(DAB\) Converter \(87 physical positions, 20 unique MPNs in total\)Full\-Bridge Switches \(Q1\-\-Q8\)Vin=48​VV\_\{\\text\{in\}\}=48\\,\\text\{V\}600​V,41​m​Ω600\\,\\text\{V\},41\\,\\text\{m\}\\OmegaIPW60R041P6FKSA1\(Infineon\)8Series Inductor \(LSER / L1\)101\.38​μ​H101\.38\\,\\mu\\text\{H\}100​μ​H100\\,\\mu\\text\{H\}ATCA\-01\-101M\-V\(ABRACON\)1Isolation Transformer \(TMAIN / T1\)Ns/Np=0\.5,Lm=420\.8​μ​HN\_\{s\}/N\_\{p\}=0\.5,L\_\{m\}=420\.8\\,\\mu\\text\{H\}4P:2S Winding Config\.HPH6\-0325L\(Coilcraft\)1In/Out Capacitors \(CIN, COUT\)20\.83​μ​F20\.83\\,\\mu\\text\{F\}22​μ​F22\\,\\mu\\text\{F\}\(450​V450\\,\\text\{V\}\)B32774D4226K\(TDK\)2Gate Drivers \(GD\_Q1\-\-GD\_Q8\)8\-Ch DriveHalf\-Bridge DriverUCC27714D\(Texas Instruments\)8Digital Controller \(CONTROL / U13\)SPS PWM Gen\.C2000 32\-bit MCUF280039CSPM\(Texas Instruments\)1Digital Isolators \(U14, U15\)Iso\. PWM InterfaceQuad\-Ch IsolatorISO7740FDWR\(Texas Instruments\)2

##### Component Selection and Control Hardware Integration\.

Within the declared nominal tolerance windows, the selection engine maps theoretical demands to commercial catalog parts and audits them against simulated reference stresses\. The base power\-stage procurement list comprises 14 component positions; after integrating the modular analog PWM controller \(UCC28C53DR\) and its application peripherals \(supply/reference decoupling,R​T/C​TRT/CTtiming, feedback divider, current\-sense RC filter, and compensation network options\), the complete hardware proposal encompasses29 physical positions across 22 unique MPNs, with 100% part\-number assignment\. The upper half of Table[3](https://arxiv.org/html/2610.38201#S4.T3)lists the core selected devices\.

Table 4:NGSPICE Reference Verification Results Across Operating Conditions for Case Study I \(Buck\) and Case Study II \(DAB\)Case \(Eval\. Window\)Test ConditionOperating PointMax StepMeanVoutV\_\{\\text\{out\}\}\(V\)MeanIoutI\_\{\\text\{out\}\}\(A\)RippleVppV\_\{\\text\{pp\}\}\(V\) / StatusBuckvin\_low24​V/6​Ω24\\,\\text\{V\}/6\\,\\Omega312\.5​ns312\.5\\,\\text\{ns\}11\.863911\.86391\.97731\.97730\.06710\.0671\(PASS\)\(6\.4–8\.0 ms\)vin\_high36​V/6​Ω36\\,\\text\{V\}/6\\,\\Omega312\.5​ns312\.5\\,\\text\{ns\}11\.836311\.83631\.97271\.97270\.06930\.0693\(PASS\)half\_load24​V/12​Ω24\\,\\text\{V\}/12\\,\\Omega312\.5​ns312\.5\\,\\text\{ns\}11\.892611\.89260\.99100\.99100\.13990\.1399\(PASS\)fine\_timestep24​V/6​Ω24\\,\\text\{V\}/6\\,\\Omega156\.25​ns156\.25\\,\\text\{ns\}11\.863911\.86391\.97731\.97730\.06700\.0670\(PASS\)DABnominal48​V/48​Ω48\\,\\text\{V\}/48\\,\\Omega\(ϕ=0\.06\\phi=0\.06\)166\.7​ns166\.7\\,\\text\{ns\}22\.742322\.74230\.47380\.47380\.17880\.1788\(PASS\)\(4\.8–6\.0 ms\)fine\_timestep48​V/48​Ω48\\,\\text\{V\}/48\\,\\Omega\(ϕ=0\.06\\phi=0\.06\)83\.3​ns83\.3\\,\\text\{ns\}22\.742222\.74220\.47380\.47380\.17950\.1795\(PASS\)

##### NGSPICE Verification and Deliverable Consistency\.

The power\-stage and gate\-driver reference circuit \(utilizing the source\-derivedti\_ucc27714\_enable\_portmodel\) was verified across four operating conditions over an8​ms8\\,\\text\{ms\}horizon \(evaluated in the final20%20\\%window,6\.4​–​8\.0​ms6\.4\\text\{\-\-\}8\.0\\,\\text\{ms\}\)\. As shown in the upper half of Table[4](https://arxiv.org/html/2610.38201#S4.T4)and Figure[3](https://arxiv.org/html/2610.38201#S4.F3)\(a\), all four test cases—low input \(24​V24\\,\\text\{V\}\), high input \(36​V36\\,\\text\{V\}\), half load \(12​Ω12\\,\\Omega\), and halved timestep \(156\.25​ns156\.25\\,\\text\{ns\}\)—passed all verification criteria\. Specifically, undervin\_low, the converter achieved a mean output voltage of11\.8639​V11\.8639\\,\\text\{V\}and a peak\-to\-peak ripple of0\.0671​Vpp0\.0671\\,\\text\{V\}\_\{\\text\{pp\}\}\(well below the0\.6​Vpp0\.6\\,\\text\{V\}\_\{\\text\{pp\}\}limit\)\. Numerical sensitivity checks between nominal and fine timesteps yielded a negligible mean voltage discrepancy of0\.0021​mV0\.0021\\,\\text\{mV\}and ripple discrepancy of0\.0498​mV0\.0498\\,\\text\{mV\}\(against a60​mV60\\,\\text\{mV\}threshold\)\. Finally, the generated KiCad schematic passed native netlist round\-trip verification \(NATIVE\_ROUNDTRIP\_CONNECTIVITY\_VERIFIED\) with83 out of 83 connected terminalsmatching the internal circuit representation exactly\.

![Refer to caption](https://arxiv.org/html/2610.38201v1/figure/buck_full_half_voltage.png)

\(a\) Non\-isolated Buck converter \(Vin=24​V,fs=80​kHzV\_\{\\text\{in\}\}=24\\,\\text\{V\},f\_\{s\}=80\\,\\text\{kHz\}\)

![Refer to caption](https://arxiv.org/html/2610.38201v1/figure/dab_full_half_voltage.png)

\(b\) Isolated DAB converter \(Vin=48​V,fs=100​kHzV\_\{\\text\{in\}\}=48\\,\\text\{V\},f\_\{s\}=100\\,\\text\{kHz\}\)

Figure 3:Simulatedngspicestartup and steady\-state output voltage \(VoutV\_\{\\text\{out\}\}\) waveforms under full\-load and half\-load operating conditions without closed\-loop feedback controllers: \(a\) Buck converter operating under a fixed PWM duty cycle at full load \(R=6​ΩR=6\\,\\Omega\) and half load \(R=12​ΩR=12\\,\\Omega\) against the12​V12\\,\\text\{V\}target; and \(b\) DAB converter operating under topology\-synthesized single\-phase\-shift \(SPS\) angles at full load \(R=48​ΩR=48\\,\\Omega, phase=21\.600∘=21\.600^\{\\circ\}\) and half load \(R=96​ΩR=96\\,\\Omega, phase=12\.843∘=12\.843^\{\\circ\}\) against the24​V24\\,\\text\{V\}target\.

### 4\.3End\-to\-End Case Study II: Isolated Dual\-Active Bridge \(DAB\) Converter

##### Design Task and Coupled Magnetic Synthesis\.

To demonstrate scalability to complex isolated bridge topologies, we prompted the system with:“DAB input 48V output 24V 0\.5A 100kHz isolated ripple 5%”\(Pout=12​WP\_\{\\text\{out\}\}=12\\,\\text\{W\}, ripple limitΔ​Vout,max=1\.2​Vpp\\Delta V\_\{\\text\{out,max\}\}=1\.2\\,\\text\{V\}\_\{\\text\{pp\}\}\)\. The DAB knowledge module applies Single\-Phase\-Shift \(SPS\) power transfer analysis, synthesizing a nominal phase\-shift ratio ofϕ=0\.06\\phi=0\.06cycles \(0\.6​μ​s0\.6\\,\\mu\\text\{s\}or21\.6∘21\.6^\{\\circ\}at100​kHz100\\,\\text\{kHz\}, with50%50\\%duty cycle and150​ns150\\,\\text\{ns\}deadtime\), a required series energy\-transfer inductance ofLser=101\.376​μ​HL\_\{\\text\{ser\}\}=101\.376\\,\\mu\\text\{H\}, and filtering capacitances ofCin=Cout=20\.833​μ​FC\_\{\\text\{in\}\}=C\_\{\\text\{out\}\}=20\.833\\,\\mu\\text\{F\}\.

Crucially, rather than assuming an idealized textbook transformer, the synthesis module selects a commercial multi\-winding transformer \(Coilcraft HPH6\-0325L\) and synthesizes a concrete physical winding configuration: four windings are connected in series on the primary side \(terminals1​–​91\\text\{\-\-\}9, bridging12​–​212\\text\{\-\-\}2,11​–​311\\text\{\-\-\}3, and10​–​410\\text\{\-\-\}4\) and two windings in series on the secondary side \(terminals5​–​75\\text\{\-\-\}7, bridging8​–​68\\text\{\-\-\}6\)\. This physical configuration realizes the exact required secondary\-to\-primary turns ratio ofNs/Np=0\.5N\_\{s\}/N\_\{p\}=0\.5and a primary magnetizing inductance ofLm=420\.8​μ​HL\_\{m\}=420\.8\\,\\mu\\text\{H\}\.

##### Component Selection, Simulation, and KiCad Verification\.

As summarized in the lower halves of Tables[3](https://arxiv.org/html/2610.38201#S4.T3)and[4](https://arxiv.org/html/2610.38201#S4.T4), the base power\-stage BOM contains 57 positions, which expands to87 enumerated physical positions across 20 unique MPNsafter integrating the digital control hardware—featuring a Texas Instruments C2000 MCU \(F280039CSPM\) with segregated3\.3​V3\.3\\,\\text\{V\}I/O and core supply decoupling, ADC sensing interfaces, and two quad\-channel digital isolators \(ISO7740FDWR\) routing eight PWM channels across the galvanic isolation barrier to eightUCC27714Dgate drivers\. Inngspice 47verification \(Figure[3](https://arxiv.org/html/2610.38201#S4.F3)\(b\)\), the nominal operating point achieved a mean output voltage of22\.7423​V22\.7423\\,\\text\{V\}\(−5\.24%\-5\.24\\%deviation from24​V24\\,\\text\{V\}, well within the±10%\\pm 10\\%open\-loop reference tolerance band\) and a peak\-to\-peak ripple of0\.1788​Vpp0\.1788\\,\\text\{V\}\_\{\\text\{pp\}\}\(0\.745%0\.745\\%, far below the5%5\\%limit\)\. Halving the maximum timestep to83\.3​ns83\.3\\,\\text\{ns\}yielded virtually identical results \(Δ​Vmean=0\.0765​mV\\Delta V\_\{\\text\{mean\}\}=0\.0765\\,\\text\{mV\}\)\. Native KiCad netlist round\-trip verification confirmed 100% connectivity fidelity across all341 out of 341 connected terminals\.

### 4\.4Comparative Evaluation: Proposed Framework vs\. Vanilla LLM

##### Experimental Protocol\.

To rigorously quantify the value of integrating domain knowledge, evidence verification, and simulation feedback, we compared our complete workflow against a one\-shot, tool\-freeVanilla LLMbaseline \(qwen3\.5\-plus\-2026\-04\-20withtemperature=0\\text\{temperature\}=0,top\_p=1\\text\{top\\\_p\}=1,max\_tokens=10000\\text\{max\\\_tokens\}=10000, andenable\_thinking=false\) on the exact same Buck and DAB design tasks\. Both methods were evaluated under identicalngspice 47testbenches and audited against source distributor/OEM documentation across eight multi\-dimensional engineering metrics\.

Table 5:Quantitative Comparison Between the Proposed Complete Workflow and the Vanilla LLM Baseline Across the Frozen Buck and DAB Benchmark Tasks
##### Quantitative Results and Diagnostic Analysis\.

As demonstrated in Table[5](https://arxiv.org/html/2610.38201#S4.T5), the proposed framework substantially outperforms the Vanilla LLM across every verification dimension:

1. 1\.Elimination of Supply\-Chain Hallucinations and Unverified Placeholders:In the warm\-library functional evaluation, our framework achieved a98\.6% \(70/71\)position verification rate and100% \(17/17\)deduplicated MPN verification rate \(with only a single Buck inductor position left unverified and transparently flagged asUNKNOWNrather than fabricated\), covering97\.0% \(162/167\)of required datasheet parameter fields\. Conversely, only22\.2% \(4/18\)of Vanilla LLM component positions could be verified against source evidence\. For the DAB magnetic components, the Vanilla LLM failed to select real commercial parts, outputting generic text placeholders \(DAB\_LEAKAGE\_INDandDAB\_XFMR\_2\_1\), whereas our framework selected verified COTS magnetics \(ATCA\-01\-101M\-VandHPH6\-0325L\) with explicit physical pin bindings\.
2. 2\.Prevention of Severe Nominal Mismatches and Voltage Rating Violations:Auditing selected part numbers against official datasheets revealed a97\.7% \(43/44\)nominal value match for our framework versus0\.0% \(0/7\)for the Vanilla LLM\. Notably, in the Buck task, the Vanilla LLM assigned resistorRC0402FR\-0710RLfor an intended10​m​Ω10\\,\\text\{m\}\\Omega\(0\.01​Ω0\.01\\,\\Omega\) capacitor ESR, whereas the actual datasheet resistance of that part number is10​Ω10\\,\\Omega—a1000×1000\\timesmagnitude error\. Even more critically, as shown in Table[6](https://arxiv.org/html/2610.38201#S4.T6), the Vanilla LLM committed severe self\-contradictory voltage rating violations: in the36​V36\\,\\text\{V\}\-input,12​V12\\,\\text\{V\}\-output Buck converter, it selected input and output capacitors \(T491A476K010ATandGRM32EC71A107KE15L\) rated at only10​V10\\,\\text\{V\}, which would cause immediate dielectric breakdown in hardware\.
3. 3\.Controller Role Mismatch:While our framework paired appropriate controllers \(UCC28C53DRandF280039CSPM\) with verified external gate drivers \(UCC27714D\), the Vanilla LLM selectedTPS54331DDCRas an “80​kHz80\\,\\text\{kHz\}timing reference” to drive an external MOSFET in the36​V36\\,\\text\{V\}Buck circuit\. However, according to Texas Instruments documentation, theTPS54331family is an integrated\-switch buck converter with a maximum input rating of28​V28\\,\\text\{V\}and a fixed570​kHz570\\,\\text\{kHz\}switching frequency—rendering it fundamentally incompatible with both the36​V36\\,\\text\{V\}bus and the80​kHz80\\,\\text\{kHz\}external\-switch architecture\.
4. 4\.Topological Connectivity and Simulation Convergence:Neither of the circuits generated by the Vanilla LLM could execute inngspice\(0% convergence\)\. Structural audits revealed that in the Vanilla Buck netlist, the positive input terminal was connected solely to the input shunt capacitor without any series power path to the switch, while the PWM voltage source and driver output simultaneously drove nodeGATE\_SIG, causing a singular matrix and “timestep too small” abort\. Similarly, the Vanilla DAB netlist left the positive output terminal isolated from the power transfer stage and misbound the stimulus port name\. In contrast, our framework achieved100% structural connectivity and simulation pass ratesacross all operating conditions \(achievingVout=11\.8839​V,Vpp=0\.0820​VV\_\{\\text\{out\}\}=11\.8839\\,\\text\{V\},V\_\{\\text\{pp\}\}=0\.0820\\,\\text\{V\}on Buckvin\_lowandVout=23\.2966​V,Vpp=0\.1562​VV\_\{\\text\{out\}\}=23\.2966\\,\\text\{V\},V\_\{\\text\{pp\}\}=0\.1562\\,\\text\{V\}on DABnominalunder the unified functional evaluation benchmark\)\.

Table 6:Diagnostic Breakdown of Representative Component and Structural Failures in Vanilla LLM vs\. Proposed Framework

## 5Discussion and Limitations

The experimental results and comparative audits demonstrate that combining domain\-specific power electronics synthesis, evidence\-backed component verification, and closed\-loop simulation advances automated design from “generating plausible part numbers” to delivering traceable, executable engineering artifacts\. Nevertheless, to maintain strict academic and engineering transparency, several scope boundaries and limitations of the current implementation warrant discussion:

1. 1\.Conservative Derating vs\. Multi\-Objective Pareto Optimization:Our current basic selection engine prioritizes provenance verifiability, rating compliance, and connectivity completeness rather than global cost, volume, or efficiency optimization\. Consequently, when querying finite local/distributor candidate pools under strict contract constraints, the engine may select conservatively over\-rated components—for instance, assigning600​V600\\,\\text\{V\}MOSFETs \(IPW60R041P6FKSA1\) and200​–​600​V200\\text\{\-\-\}600\\,\\text\{V\}film/electrolytic capacitors in the24​–​48​V24\\text\{\-\-\}48\\,\\text\{V\}Buck and DAB cases \(yielding safety ratios of7\.8×7\.8\\timesto16\.1×16\.1\\timesabove minimum derated thresholds\)\. While electrically safe for functional prototyping, future extensions will incorporate multi\-objective cost, footprint, and switching\-loss \(Qg×RD​S​\(on\)Q\_\{g\}\\times R\_\{DS\(\\text\{on\}\)\}\) Pareto ranking\.
2. 2\.Simulation Model Fidelity Hierarchy and Closed\-Loop Control:In our default verification path, time\-domainngspicewaveforms validate externally modulated power stages and source\-derived gate\-driver adapters using parameterized behavioral semiconductor models, while modular controller hardware \(e\.g\.,UCC28C53DR,F280039CSPM\) is synthesized separately for schematic connectivity\. Thus, passing power\-stage reference simulation does not constitute full\-system closed\-loop stability proof, DSP firmware validation, or electro\-thermal Safe Operating Area \(SOA\) qualification\.
3. 3\.Sample Size and Component Coverage Gaps:Even within the full framework, certain specialized passive positions \(such as the Buck inductor under strict current\-saturation evidence requirements in the comparative audit\) may remain unverified \(UNKNOWN\) when local datasheet evidence is incomplete, highlighting the need for broader distributor API and multimodal datasheet coverage\. Furthermore, while the two\-case comparison clearly exposes structural and parametric failure modes of one\-shot LLMs, expanding the benchmark to larger query sets and multi\-turn tool\-assisted baselines remains an important direction for future statistical evaluation\.

## 6Conclusion and Future Work

In this paper, we presented aBounded Dual\-Loop Automated Schematic Synthesis Frameworkthat translates unstructured natural language specifications into verified, editable power electronics hardware deliverables\. Rather than relying on open\-loop text generation, our workflow coordinates domain\-knowledge\-driven circuit synthesis \(covering Buck, Boost, Flyback, DAB, and half\-bridge LLC topologies\), contract\- and evidence\-backed commercial component selection, and closed\-loopngspiceverification with stress feedback, culminating in modular control hardware integration and nativeKiCadnetlist round\-trip verification\. End\-to\-end demonstrations on a24​–​36​V24\\text\{\-\-\}36\\,\\text\{V\}to12​V/2​A12\\,\\text\{V\}/2\\,\\text\{A\}Buck converter \(29 positions, 83 verified terminals\) and an isolated48​V48\\,\\text\{V\}to24​V/0\.5​A24\\,\\text\{V\}/0\.5\\,\\text\{A\}DAB converter \(87 positions, 341 verified terminals\) confirm the framework’s ability to produce synchronized design reports, production BOMs, SPICE netlists, and 100% connectivity\-verified schematics\. Comparative evaluations against a one\-shot Vanilla LLM baseline further demonstrate improvements in component evidence verification from22\.2%22\.2\\%to98\.6%98\.6\\%, datasheet nominal\-value consistency from0\.0%0\.0\\%to97\.7%97\.7\\%, and SPICE simulation pass rates from0\.0%0\.0\\%to100\.0%100\.0\\%\.

This work demonstrates that reliable AI\-assisted hardware engineering lies in orchestrating semantic model comprehension with symbolic domain solvers, real\-world supply\-chain evidence, and physical simulators\. Building upon the verification boundaries established in this study, our future work will focus on two primary directions:

1. 1\.Multi\-Objective Component Optimization and High\-Fidelity Electro\-Thermal Verification:To move beyond conservative derating margins and behavioral switch approximations, we plan to integrate real\-time pricing, footprint constraints, and semiconductor loss figures\-of\-merit \(RD​S​\(on\)×QgR\_\{DS\(\\text\{on\}\)\}\\times Q\_\{g\}\) for Pareto\-optimal component selection, while binding vendor\-specific nonlinear SPICE subcircuits to qualify Safe Operating Area \(SOA\) and soft\-switching \(ZVS/ZCS\) boundaries\.
2. 2\.Closed\-Loop Control Synthesis and Layout\-Aware PCB Realization:We aim to extend the modular control stage from pin\-level hardware connectivity to automated small\-signal compensator sizing and digital control firmware generation, while coupling custom magnetic design with automated KiCad PCB layout synthesis to close the loop between schematic verification and parasitic\-aware physical implementation\.

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