eda

Prism is a new product described as "Cursor for hardware engineering," an AI-assisted tool aimed at hardware/EDA workflows.

Tsinghua University researchers propose a Bounded Dual-Loop Automated Schematic Synthesis Framework that converts natural language specifications into verified KiCad schematics for power electronics, boosting component verification coverage from 22.2% to 98.6% and SPICE pass rates from 0% to 100% versus a vanilla LLM baseline.

We present TACS-RF, a framework where an LLM coding agent (Claude Opus 4.8) semi-autonomously drives industry-standard EDA tools to design a 240-251 GHz sub-THz transmitter in 90 nm SiGe BiCMOS, marking a step toward a 'text-to-ASIC' future for RF/mmWave hardware design.

该论文首次提出基于多目标强化学习的 LLM RTL 电路生成方法，通过 Hypervolume Contribution 奖励优化整组电路的 PPA 权衡多样性，在 RTLLM v2 基准上较单目标 RL 基线提升 14.4 个百分点的相对超体积。

siliXon 是一款新产品，能通过自然语言描述自动生成可制造的 PCB 电路板设计，其设计代理 Rocky 负责选型、布局、绘制原理图和布线，并通过工程检查后交付设计文件。

HarnessHive 是面向线束工程师的 AI 原生设计生态，将原理图、布局、BOM 和按比例输出的 formboard 集成到一个实时协作文档中，并内置 AI 助手辅助每一步设计流程。该产品在 Product Hunt 上发布。

一条推文展示了一个在 VS Code 中运行的 AI 工具链自动完成 135 元件、514 焊盘、4 层 PCB 的设计——计算元件、读取数据手册并绘制原理图，体现了 AI 正在降低硬件开发门槛。

一篇提出 AI 驱动、时序感知的芯片后布线功耗优化框架的论文，使用梯度提升模型集成对功耗修复编辑和修复动作进行排序，同时由确定性 EDA 分析把关约束。论文给出契约与预注册评估协议，但尚未报告训练模型的结果。

A developer commentary arguing that chip design is fundamentally a massive combinatorial search problem — with 500,000 standard cells yielding ~10^2,632,341 arrangements, dwarfing Go or protein folding — and that AI could lower the cost of exploring that space, leading to more custom silicon tape-outs rather than fewer.

OpenAI and Synopsys announce a multi-year partnership to co-develop GPT-Synopsys, a specialized frontier model trained to natively operate Synopsys EDA tools and accelerate semiconductor design, with a shared revenue and go-to-market framework.

This paper proposes Population-Curated Policy Optimization (PCPO), a sample-efficient parametric self-evolution method that helps LLM algorithm-design agents escape in-context evolutionary stagnation by training on self-generated algorithms. Trained on only 4 chip cases, PCPO outperforms OpenEvolve and ShinkaEvolve across 16 EDA cases, matches GPT-5.5 with an 8B model, and achieves 8.27× average speedup on GPU kernel design.

ChipMEM introduces a verification-grounded memory layer for EDA agents, enhancing RTL design performance by distilling reusable skills from verified tool interactions and using Bayesian statistical guidance for transfer to unseen tasks.

This paper presents TARGet, a topology-aware fusion-based method using graph neural networks for radio frequency circuit functional modeling, demonstrating improved prediction accuracy and data efficiency over state-of-the-art approaches.

This paper presents ZhuLong, an execution-grounded LLM coding agent for EDA scripting that uses API retrieval, documentation inspection, and sandbox execution via MCP tools, augmented by an offline API self-exploration mechanism to infer undocumented API behaviors. It achieves 78.5% Pass@1 on a benchmark of 158 real-world EDA tasks, significantly outperforming a pure LLM baseline.

NVIDIA is collaborating with Cadence and Synopsys to optimize EDA applications for its Vera CPU, achieving up to 1.5x performance improvement in chip design workflows for next-generation CPUs and GPUs.

RF-Agent introduces a textbook-driven knowledge distillation pipeline to create the first RF-domain reasoning dataset and benchmark, demonstrating that domain-specific fine-tuning and semantic retrieval significantly improve LLM reasoning for RF circuit design.

A technical deep-dive explaining what a memory compiler is, how it uses bitcells to generate SRAM layouts, and the design concepts involved from cross-coupled inverters to GDS tiling.

KiCad, the open-source PCB EDA suite, is now available in the browser via PCBJam from Emergence Engineering, using WebAssembly, WebGL, and threaded emulation to achieve near-native performance.

SwiftCTS is a physics-informed surrogate framework that uses gradient-boosted ensembles and few-shot calibration to rapidly predict and Pareto-optimize clock tree metrics (power, wirelength, timing skew) across unseen designs, achieving high accuracy with minimal training data.

Alpha-RTL (TTT-RTL) introduces a test-time training framework for RTL hardware optimization, using reinforcement learning with EDA feedback to refine LLM-generated designs. It achieves significant PPA reductions on benchmarks.