NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs

NVIDIA Blog 07/27/26, 12:45 AM News

nvidia vera-cpu eda chip-design cadence synopsys cpu-acceleration

Summary

NVIDIA is collaborating with Cadence and Synopsys to optimize EDA applications for its Vera CPU, achieving up to 1.5x performance improvement in chip design workflows for next-generation CPUs and GPUs.

<div id="bsf_rt_marker"></div>The complexity of modern chip design continues to grow as engineering teams work to develop increasingly sophisticated CPUs, GPUs and AI systems. To help meet that challenge, <a target="_blank" href="https://nvidianews.nvidia.com/news/nvidia-expands-nvidia-agent-toolkit-with-nvidia-physicsnemo-and-cuda-x-libraries-to-transform-how-the-world-engineers-designs-and-builds">NVIDIA is collaborating with industry leaders Cadence and Synopsys</a> to optimize critical electronic design automation (EDA) applications for the NVIDIA Vera CPU. NVIDIA is now deploying Vera across EDA workflows used to develop its next generation of CPUs and GPUs, demonstrating how high-performance CPU architecture can help accelerate some of the industry’s most demanding engineering workloads. <h2>Accelerating Critical EDA Workloads</h2> What’s at stake is the pace of chip production. In turn, the tempo of industry technologies that stand to benefit from boosted EDA workloads, driving development momentum. Simulation, verification and implementation technologies play a central role in semiconductor development. Long before a chip reaches manufacturing, engineers spend years validating behavior, identifying corner cases and refining designs through thousands of iterations. While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance. Logic simulation, formal verification and portions of digital implementation often depend on fast individual cores, efficient memory systems and strong overall throughput. That makes CPU architecture an important factor in determining how quickly engineering teams can validate designs, explore alternatives and move products toward tapeout.   <figure id="attachment_96871" aria-describedby="caption-attachment-96871" style="width: 960px" class="wp-caption alignnone"><img fetchpriority="high" decoding="async" class="size-medium wp-image-96871" src="https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-960x720.jpeg" alt="" width="960" height="720" srcset="https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-960x720.jpeg 960w, https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-1680x1261.jpeg 1680w, https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-1280x960.jpeg 1280w, https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-1536x1153.jpeg 1536w, https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-630x473.jpeg 630w, https://blogs.nvidia.com/wp-content/uploads/2026/07/image3.jpeg 1999w" sizes="(max-width: 960px) 100vw, 960px" /><figcaption id="caption-attachment-96871" class="wp-caption-text">Vera cluster in NVIDIA Portland data center.</figcaption></figure> <h2>Highlighting Early Results With Cadence and Synopsys</h2> NVIDIA’s initial testing includes several leading EDA applications. The results highlight Vera’s ability to accelerate two of the most compute-intensive stages of modern chip design. Early testing on selected production-class workflows shows promising results. Cadence Jasper, a formal verification platform, uses smart proof technology and machine learning to find and fix bugs and improve verification productivity early in the design cycle. Synopsys VCS, a high-performance functional verification solution used to simulate and validate complex chip designs before fabrication, used the same number of cores in the test. Both applications showed up to 1.5x higher performance on selected workloads. Beyond benchmark results, NVIDIA is working closely with both companies on application profiling, software optimization and system-level tuning designed to improve engineering productivity across a broader range of workflows over time. <h2>Bringing Vera to the Design Process</h2> NVIDIA is deploying Vera throughout the EDA workflows used to create future NVIDIA processors. Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric designed to deliver strong per-core performance, high memory bandwidth and consistent low latency for demanding engineering applications. These capabilities are particularly important for workloads that mix latency-sensitive jobs with large-scale regression testing across compute farms. Faster execution can shorten individual verification runs, while greater throughput enables engineers to evaluate more design alternatives and complete more validation within the same development window. <h2>Going From RTL to Silicon</h2> After defining a processor’s architecture and microarchitecture, engineers describe much of its behavior at the register-transfer level (RTL). Multiple verification and implementation technologies then work together to transform that design into manufacturable silicon. These workflows span logic simulation, formal verification, regression testing and digital implementation, helping engineers validate functionality, identify corner cases and transform designs into manufacturable silicon. Because these stages are interconnected, improvements in verification throughput can help organizations identify issues earlier and reduce costly downstream design iterations. <h2>Building Future NVIDIA Chips With NVIDIA CPUs</h2> The deployment of Vera across NVIDIA’s own engineering workflows reflects a broader strategy: accelerate each workload with the compute architecture best suited to the task. In EDA, GPUs and AI continue to speed many algorithms, while high-performance CPUs remain essential for critical simulation, verification and implementation workloads. Together, they help improve the performance of the overall design cycle. Looking ahead, NVIDIA plans to build on Vera with the next-generation Rosa CPU, powered by the NVIDIA Rigel core, while continuing to optimize leading EDA applications across its CPU roadmap. By using NVIDIA CPUs to help design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering, with each generation helping build the next. Learn more about NVIDIA at <a target="_blank" href="https://www.nvidia.com/en-us/events/dac/">DAC 2026</a>.

Original Article

View Cached Full Text

Cached at: 07/27/26, 01:44 AM

# NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs Source: [https://blogs.nvidia.com/blog/vera-cpu-eda/](https://blogs.nvidia.com/blog/vera-cpu-eda/) The complexity of modern chip design continues to grow as engineering teams work to develop increasingly sophisticated CPUs, GPUs and AI systems\. To help meet that challenge,[NVIDIA is collaborating with industry leaders Cadence and Synopsys](https://nvidianews.nvidia.com/news/nvidia-expands-nvidia-agent-toolkit-with-nvidia-physicsnemo-and-cuda-x-libraries-to-transform-how-the-world-engineers-designs-and-builds)to optimize critical electronic design automation \(EDA\) applications for the NVIDIA Vera CPU\. NVIDIA is now deploying Vera across EDA workflows used to develop its next generation of CPUs and GPUs, demonstrating how high\-performance CPU architecture can help accelerate some of the industry’s most demanding engineering workloads\. ## **Accelerating Critical EDA Workloads** What’s at stake is the pace of chip production\. In turn, the tempo of industry technologies that stand to benefit from boosted EDA workloads, driving development momentum\. Simulation, verification and implementation technologies play a central role in semiconductor development\. Long before a chip reaches manufacturing, engineers spend years validating behavior, identifying corner cases and refining designs through thousands of iterations\. While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance\. Logic simulation, formal verification and portions of digital implementation often depend on fast individual cores, efficient memory systems and strong overall throughput\. That makes CPU architecture an important factor in determining how quickly engineering teams can validate designs, explore alternatives and move products toward tapeout\. ![](https://blogs.nvidia.com/wp-content/uploads/2026/07/image3-960x720.jpeg)*Vera cluster in NVIDIA Portland data center\.*## **Highlighting Early Results With****Cadence****and****Synopsys** NVIDIA’s initial testing includes several leading EDA applications\. The results highlight Vera’s ability to accelerate two of the most compute\-intensive stages of modern chip design\. Early testing on selected production\-class workflows shows promising results\. Cadence Jasper, a formal verification platform, uses smart proof technology and machine learning to find and fix bugs and improve verification productivity early in the design cycle\. Synopsys VCS,a high\-performance functional verification solution used to simulate and validate complex chip designs before fabrication, used the same number of cores in the test\. Both applications showed up to 1\.5x higher performance on selected workloads\. Beyond benchmark results, NVIDIA is working closely with both companies on application profiling, software optimization and system\-level tuning designed to improve engineering productivity across a broader range of workflows over time\. ## **Bringing Vera to the Design Process** NVIDIA is deploying Vera throughout the EDA workflows used to create future NVIDIA processors\. Vera combines 88 custom NVIDIA Olympus CPU cores with a high\-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric designed to deliver strong per\-core performance, high memory bandwidth and consistent low latency for demanding engineering applications\. These capabilities are particularly important for workloads that mix latency\-sensitive jobs with large\-scale regression testing across compute farms\. Faster execution can shorten individual verification runs, while greater throughput enables engineers to evaluate more design alternatives and complete more validation within the same development window\. ## **Going From RTL to Silicon** After defining a processor’s architecture and microarchitecture, engineers describe much of its behavior at the register\-transfer level \(RTL\)\. Multiple verification and implementation technologies then work together to transform that design into manufacturable silicon\. These workflows span logic simulation, formal verification, regression testing and digital implementation, helping engineers validate functionality, identify corner cases and transform designs into manufacturable silicon\. Because these stages are interconnected, improvements in verification throughput can help organizations identify issues earlier and reduce costly downstream design iterations\. ## **Building Future NVIDIA Chips With NVIDIA CPUs** The deployment of Vera across NVIDIA’s own engineering workflows reflects a broader strategy: accelerate each workload with the compute architecture best suited to the task\. In EDA, GPUs and AI continue to speed many algorithms, while high\-performance CPUs remain essential for critical simulation, verification and implementation workloads\. Together, they help improve the performance of the overall design cycle\. Looking ahead, NVIDIA plans to build on Vera with the next\-generation Rosa CPU, powered by the NVIDIA Rigel core, while continuing to optimize leading EDA applications across its CPU roadmap\. By using NVIDIA CPUs to help design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering, with each generation helping build the next\. *Learn more about NVIDIA at*[*DAC 2026*](https://www.nvidia.com/en-us/events/dac/)*\.*

NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs

Similar Articles

NVIDIA Vera CPU Is ‘Packing a Heavy-Hitting Punch’ Against Competition

NVIDIA just dropped their new Vera CPUs — apparently 2x faster than x86

NVIDIA Vera CPU Opens the Way for Agentic Scientific AI at Los Alamos National Laboratory

AI Innovators Adopt NVIDIA Vera — Why Max Single-Threaded CPU at Scale Matters

Vera Arrives: NVIDIA’s First CPU Built for Agents Lands at Top AI Labs

Submit Feedback

Similar Articles

NVIDIA Vera CPU Is ‘Packing a Heavy-Hitting Punch’ Against Competition

NVIDIA just dropped their new Vera CPUs — apparently 2x faster than x86

NVIDIA Vera CPU Opens the Way for Agentic Scientific AI at Los Alamos National Laboratory

AI Innovators Adopt NVIDIA Vera — Why Max Single-Threaded CPU at Scale Matters

Vera Arrives: NVIDIA’s First CPU Built for Agents Lands at Top AI Labs