How to Look at HBM with an Industry Chain Mindset? Which Companies Should We Focus On?

After scrolling through Twitter, I found nothing but shilling and PnL screenshots – no one clearly explains the entire HBM supply chain. Using the mindset of @aleabitoreddit, only by understanding the industry chain can we know what to buy and what not to buy. Let me give everyone a crash course today.

What is HBM?

HBM stands for High Bandwidth Memory. It vertically stacks multiple layers of DRAM using Through-Silicon Vias (TSV), achieving extremely high memory bandwidth and low latency. This provides massive data throughput for AI GPUs like NVIDIA’s, breaking through the “memory wall” bottleneck of traditional memory.

What Are the Core Technologies of HBM?

Simply put, HBM uses stacking technology to vertically stack multiple DRAM dies. The most important process is TSV (Through-Silicon Via). Here, TSV drilling is not simply done by laser; instead, etching gases continuously etch downward through the silicon wafer to create holes in the dies, which are then filled with copper. After the copper-filled holes are formed, a layer of tin (micro-bumps) is added on top, allowing multiple bare dies to be stacked together.

The four most important parts in this process are:

• HBM Design & Manufacturing: Done by SK hynix, Micron, and Samsung Electronics themselves.
• TSV Drilling Equipment: Monopolized by Applied Materials (AMAT) and Lam Research (LRCX).
• Etching/Deposition/Polishing Materials: Entegris ($ENTG).
• HBM Test Probe Cards: FormFactor ($FORM) – a deep partner of SK hynix.

However, if only stacked, the dies are suspended except for the micro-bump connections and are very fragile. For reinforcement and heat dissipation, the three major manufacturers currently have two solutions:

• SK hynix first stacks the entire HBM, then places it into a mold and fills the gaps with liquid epoxy resin. After that, heat and pressure are applied to cure the epoxy resin.
• Samsung and Micron add a polymer film between two layers of chips. During heating and pressurization, the film at the micro-bump positions melts, completing the soldering, and then solidifies upon cooling. This process is repeated layer by layer.

Between the two, SK hynix’s method is better because there is no interference during the micro-bump soldering, resulting in better manufacturing speed and yield.

For heat dissipation, SK hynix also mixes thermally conductive particles into the epoxy resin, effectively turning the epoxy into something similar to thermal paste. SK hynix’s heat dissipation efficiency is twice that of Samsung, which is why SK hynix’s market share can reach 50%.

So, if you have SK hynix ADR, directly swap your MU holdings for SK hynix.

HBM Integration and Packaging – CoWoS

After HBM is manufactured, the next step is connecting it to the GPU. In traditional circuit boards, chips are connected via circuits etched on the PCB. However, the communication lines between HBM and GPU are extremely dense; ordinary PCB circuit densities simply cannot achieve that. Therefore, TSMC ($TSM) introduced a 2.5D packaging method called CoWoS (Chip-on-Wafer-on-Substrate).

The principle is to use a lithography machine to directly etch the interconnecting circuits between HBM and GPU onto a large silicon interposer (line spacing can be as small as 0.8~2μm), and then solder both chips together at once. This meets both high bandwidth and low latency requirements. NVIDIA’s H100 and B200 both use this method.

What is CoPoS?

Simply put, current silicon wafers are expensive and round, while mainstream chips are square, leading to waste when dicing the circular wafer. Some have proposed arranging chips on a square “panel RDL layer” to replace the original round silicon interposer, enhancing the interconnect layout between different conductive layers and materials. By introducing new materials like glass or sapphire, the square format allows packaging multiple chips of different sizes simultaneously, supports larger reticle limits, and alleviates warpage issues that worsen with larger chips.

However, interconnect density is currently somewhat lower, and panel-level tools and yields are still under development, still in trial production/introduction phase – not as maturely mass-produced as CoWoS.

These advanced packaging technologies mainly depend on TSMC (TSM) and Amkor (AMKR). On June 16, these two companies signed a 10-year agreement, proving that capacity in this area is indeed insufficient.

CoWoS is the current workhorse (2.5D), while CoPoS + glass substrates are the next-generation large-format direction. TSMC flexibly combines them through its 3DFabric platform, covering packaging needs from AI to mobile devices.

Currently, TSV drilling equipment, HBM testing, and CoWoS still present good opportunities.

The above is solely personal analysis and not investment advice. DYOR~