Tag
We present TACS-RF, a framework where an LLM coding agent (Claude Opus 4.8) semi-autonomously drives industry-standard EDA tools to design a 240-251 GHz sub-THz transmitter in 90 nm SiGe BiCMOS, marking a step toward a 'text-to-ASIC' future for RF/mmWave hardware design.
NVIDIA is collaborating with Cadence and Synopsys to optimize EDA applications for its Vera CPU, achieving up to 1.5x performance improvement in chip design workflows for next-generation CPUs and GPUs.