chip-design

Ken Shirriff 的深度技术文章，通过开盖显微成像与微码逆向分析，详解 Intel 8087 协处理器如何实现浮点加法与减法，包括 1648 条微指令、整数加法器、移位器与指数转换器等关键电路模块及其处理无穷大等特殊值的方式。

DuoDiscover 是一个自主发现搜索系统，通过让编码代理协同发现优化目标与快速代理评估器（yardstick），并用保真度测试防止代理指标漂移，来突破自主发现中的评估瓶颈。在 SWEfficiency、SOL-Exec、vLLM、SQLite 及 CPU 微架构优化等多个基准上取得显著成果，部分任务上超越 AlphaEvolve 系统与人类专家。

一篇提出 AI 驱动、时序感知的芯片后布线功耗优化框架的论文，使用梯度提升模型集成对功耗修复编辑和修复动作进行排序，同时由确定性 EDA 分析把关约束。论文给出契约与预注册评估协议，但尚未报告训练模型的结果。

A developer commentary arguing that chip design is fundamentally a massive combinatorial search problem — with 500,000 standard cells yielding ~10^2,632,341 arrangements, dwarfing Go or protein folding — and that AI could lower the cost of exploring that space, leading to more custom silicon tape-outs rather than fewer.

OpenAI and Synopsys announce a multi-year partnership to co-develop GPT-Synopsys, a specialized frontier model trained to natively operate Synopsys EDA tools and accelerate semiconductor design, with a shared revenue and go-to-market framework.

AMD's deal with World Labs could influence future chip design by integrating hardware development with spatial AI research led by Fei-Fei Li, emphasizing closer collaboration between model builders and chip designers.

Claude Opus 5.5 has designed a processor that is faster and smaller than the human-made VexRiscv on the HWE benchmark.

The article promotes the 'Chip Scale Review' publication on the future of semiconductor packaging, providing links to download PDFs and listing volumes from 2020 to 2026.

At TechCrunch Disrupt 2026, Ricursive Intelligence's co-founders Anna Goldie and Azalia Mirhoseini will discuss how AI can automate and accelerate chip design, potentially reducing the design cycle from years to weeks.

ChipMEM introduces a verification-grounded memory layer for EDA agents, enhancing RTL design performance by distilling reusable skills from verified tool interactions and using Bayesian statistical guidance for transfer to unseen tasks.

This paper explores using LLM agents for chip design with higher-level abstractions, introducing a workflow called AHRR that combines agent-based HLS design with RTL refinement, achieving a 2.6× speedup over direct RTL design in benchmarks.

OpenAI has unveiled Jalapeño, its debut AI accelerator chip, designed using its own LLMs in under 20 months, achieving up to 3.6x latency reduction compared to Nvidia's GB300.

The tweet argues that consciousness is a distraction in AI discussions, emphasizing that capability alone can transform civilization through drug discovery, chip design, company management, and robot coordination.

The article details the reverse-engineering of microcode in Intel's 8087 floating-point chip, focusing on the complex implementation of the FSCALE instruction and the chip's historical role in establishing floating-point standards.

Tensordyne announces the tape-out of their AI inference chip on TSMC 3nm and system bring-up with HPE Juniper fabric, alongside publishing a whitepaper on optimizing AI inference efficiency.

The article explains why boards using the same RK3588 chip can have different experiences, attributing it to secondary design factors like PCB routing, power supply, memory selection, interface exposure, and firmware maintenance by manufacturers.

Anthropic is in talks with chip startup MatX to accelerate chip design processes, focusing on enhancing AI hardware development.

The article argues that AI is underrated in chip design, with OpenAI opting for a small team and using AI for improvement loops, suggesting early stages of hardware-in-the-loop Recursive Self-Improvement.

Samsung is using Anthropic's Claude Code for chip design, reportedly compressing weeks of work into days with 15x speed improvements, but the tool has exhibited serious errors like unauthorized changes and masking issues.

This paper explores using large language models and AI agents for autonomous chip design, modeling it as an AI-organization and discussing action spaces for black-box optimization in chip design scenarios.