eda

ChipMEM introduces a verification-grounded memory layer for EDA agents, enhancing RTL design performance by distilling reusable skills from verified tool interactions and using Bayesian statistical guidance for transfer to unseen tasks.

This paper presents TARGet, a topology-aware fusion-based method using graph neural networks for radio frequency circuit functional modeling, demonstrating improved prediction accuracy and data efficiency over state-of-the-art approaches.

This paper presents ZhuLong, an execution-grounded LLM coding agent for EDA scripting that uses API retrieval, documentation inspection, and sandbox execution via MCP tools, augmented by an offline API self-exploration mechanism to infer undocumented API behaviors. It achieves 78.5% Pass@1 on a benchmark of 158 real-world EDA tasks, significantly outperforming a pure LLM baseline.

NVIDIA is collaborating with Cadence and Synopsys to optimize EDA applications for its Vera CPU, achieving up to 1.5x performance improvement in chip design workflows for next-generation CPUs and GPUs.

RF-Agent introduces a textbook-driven knowledge distillation pipeline to create the first RF-domain reasoning dataset and benchmark, demonstrating that domain-specific fine-tuning and semantic retrieval significantly improve LLM reasoning for RF circuit design.

A technical deep-dive explaining what a memory compiler is, how it uses bitcells to generate SRAM layouts, and the design concepts involved from cross-coupled inverters to GDS tiling.

KiCad, the open-source PCB EDA suite, is now available in the browser via PCBJam from Emergence Engineering, using WebAssembly, WebGL, and threaded emulation to achieve near-native performance.

SwiftCTS is a physics-informed surrogate framework that uses gradient-boosted ensembles and few-shot calibration to rapidly predict and Pareto-optimize clock tree metrics (power, wirelength, timing skew) across unseen designs, achieving high accuracy with minimal training data.

Alpha-RTL (TTT-RTL) introduces a test-time training framework for RTL hardware optimization, using reinforcement learning with EDA feedback to refine LLM-generated designs. It achieves significant PPA reductions on benchmarks.

RTL-BenchMT is an agentic framework that automatically identifies and revises flawed cases and detects overfitting in RTL generation benchmarks, reducing human maintenance effort in EDA research.

NVIDIA researchers present the first self-evolving logic synthesis framework where multi-agent LLMs autonomously refine the ABC EDA tool codebase.