risc-v

Pine64 launched the PineVoice, a $50 RISC-V smart speaker designed for Home Assistant tinkerers, featuring open-source firmware and local voice control via the Wyoming protocol.

QSOE 0.1, a QNX-inspired operating system with selectable kernels (Skimmer microkernel or seL4), has been released. It targets 64-bit RISC-V hardware and is available under Apache-2.0.

Yuri Zaporozhets of QRV Systems has built a RISC-V-based personal computer and a mainframe on an FPGA, and rewritten QNX twice. His latest OS QSOE is gaining attention in the FOSS world.

QSOE project v0.1 is released, providing a QNX-compatible operating system with two microkernel variants (custom Skimmer kernel and seL4-based), shared userspace, and support for SiFive Unmatched RISC-V hardware.

Review of the MilkV Jupiter 2 single-board computer featuring the SpacemiT K3 RISC-V SoC with 16 cores and vector compute, exploring its capabilities for running AI inference workloads.

Espressif announced the ESP32-S31, a dual-core RISC-V SoC with Wi-Fi 6, Bluetooth 5.4 LE, Ethernet, and advanced security features, targeting IoT and multimedia applications.

A detailed guide on connecting a JLink JTAG probe to the Pinecil soldering iron via its breakout board to enable hardware debugging of the Bouffalo Lab BL706 MCU (SiFive E24 core) using JLinkGDBServer and GDB, particularly useful for Zephyr RTOS development.

The author open-sourced a custom AI accelerator (atik) implemented on FPGA with native BF16 and attention support, demonstrating significant speedups over PyTorch for various models.

ByteDance is developing custom CPUs using Arm and RISC-V architectures to support its AI infrastructure and reduce reliance on Intel and AMD due to long processor delivery times.

Riscrithm is a high-level macro-assembly dialect for RISC-V, written in Go, that compiles readable code into pure RISC-V assembly with optional optimization.

Demonstrates running a DCGAN with 12.6M int8 quantized parameters on a low-cost RISC-V microcontroller (CH32H417), generating 64x64 cat faces in 26 seconds using pure C inference and quantum entropy sampling.

A report on the RISC-V architecture's floating point capabilities and updates.

Espressif's open-source hands-on ESP32-C3 development guide with code examples for IoT projects, covering hardware, connectivity, and low-power optimization.

A crowdfunding campaign for a RISC-V based router is currently at 10% of its goal with 89 contributors.

Sipeed's new K3 RISC-V single-board computers feature 32GB LPDDR5 and a 60 TOPS NPU, enabling local inference of large language models at up to 15 tokens per second.

Introduces EMiX, a scalable multi-FPGA framework for emulating multi-core RISC-V architectures beyond single-FPGA resource limits, demonstrated with a 64-core system across eight FPGAs.

A tutorial on building an autonomous AI agent on a $15 RISC-V device (LicheeRV Nano) that can manage its own Lightning Network wallet and make autonomous Bitcoin payments via Nostr.