China’s Memory Industry Can No Longer Be Summed Up as “Generations Behind”

In the past, any discussion about China’s memory industry inevitably circled back to one question: how many generations behind are CXMT and YMTC compared with Samsung, SK Hynix, and Kioxia?

That framing was popular for many years, and it did make sense at the time. Memory is an extremely unforgiving scale-driven industry. Fall one process generation behind, and per-unit costs rise noticeably; miss yield targets by a few percentage points, and a multi-billion-dollar fab can go from printing money to burning it. Ranking players by process node, layer count, capacity, and production scale was simple and intuitive.

But today, that yardstick no longer measures things accurately.

The memory industry is undergoing a change that is not particularly noisy but is quite profound. In the past, the competition was about who could shrink line widths further and stack NAND higher. Now, pure scaling is getting increasingly difficult, and manufacturers are beginning to rearrange the placement of transistors, memory arrays, and peripheral circuits. Planar structures are being stood upright. Things once fabricated on a single wafer are being split across two wafers, manufactured separately, and then bonded back together.

In other words, competition is shifting from “who can run faster along the old route” to “who can first find a new route and turn it into a stable product.” It is precisely at this inflection point that China’s position in the memory industry has changed.

This is not to say China has comprehensively overtaken Japan and South Korea. At least in the HBM market — the most profitable segment today — Korea still stands at the forefront. Samsung has already announced HBM4 mass production and customer shipments, and SK Hynix’s accumulated depth in HBM, advanced DRAM, packaging, and GPU customer collaboration far exceeds that of Chinese manufacturers. China still has a long way to go in HBM yield, advanced packaging, and certification from top-tier international customers.

But another statement repeated for years should also be discarded: that China’s memory industry can only chase behind Japan and South Korea.

Because in next-generation memory architectures, China is no longer just a follower.

What CXMT Has Delivered Is More Than Just Another DRAM

CXMT can now mass-produce DDR5 and LPDDR5X. According to the company’s disclosures, 8533Mbps and 9600Mbps LPDDR5X entered mass production in May 2025, and the 10667Mbps product has been sampled to customers. These products certainly matter — they mean China’s DRAM is moving from “whether it exists at all” to head-on competition in performance, cost, and customer qualification.

However, what truly makes me feel that the industry’s landscape is shifting is not these catch-up products, but a paper published at IEEE IMW 2023.

In that paper, CXMT and Beijing Superstring demonstrated an 8Gb full-array vertical channel transistor DRAM with a public density of 198Mbit/mm². The most noteworthy thing here is not some impressive parameter, but the phrase “8Gb full-array silicon verification.” This is not about fabricating a single switching transistor in a lab; it is about organizing a large number of cells into an array and getting the entire structure to work on silicon.

This technology points to 4F² DRAM.

Today’s common DRAM cells occupy roughly 6F² of area. F can be understood as the minimum feature size in a process. If cell area shrinks from 6F² to 4F², the cell footprint decreases by one-third in the ideal case, allowing roughly 50% more memory cells in an array of the same size. Considering peripheral circuits, routing, and redundancy, the density of the entire chip will not mechanically increase by 50%, but this is still enough to rewrite the future cost curve of DRAM.

The truly difficult part of 4F² is not about drawing two fewer squares on the layout. Traditional transistors are increasingly cramped on a planar surface. To shrink the cell further, the channel or gate must be turned vertical, and then bit lines, contacts, capacitors, and leakage issues must all be re-engineered. How to form buried bit lines, how to achieve self-aligned contact holes, whether an oxide channel can balance drive current with retention time — any one of these can stall mass production.

That is precisely why the 8Gb full-array silicon verification from CXMT carries weight.

Now look at the public progress of Japanese and Korean manufacturers. When SK Hynix announced its future DRAM roadmap in 2025, it indicated it was considering a shift from 10nm-class and below technologies to a 4F² vertical gate platform. As of 2026, the company was still strengthening a dedicated VG R&D team. In Japan, Kioxia and Nanya demonstrated a 4F² OCTRAM prototype at IEDM 2024, with quite impressive device performance, but at its 2026 Investor Day, Kioxia still described it as a research project evaluating market feasibility and mass-production readiness.

So how should CXMT’s lead be understood? Not that it has already flooded the market with 4F² DRAM, and not that Samsung and SK Hynix cannot do it. Rather, among currently publicly verifiable information, China has already crossed the threshold of full-array silicon verification relatively early.

From a single transistor to an array, and from an array to mass production, there is still a long road ahead. But at least at the starting position, China is not trailing this time.

YMTC Has Gone Further, Because It Has Already Mass-Produced a New Architecture Once

If 4F² proves China has taken a front-row seat in next-generation DRAM research, then Xtacking’s significance is even more direct: it proves a Chinese company can not only propose a new architecture but also push it into production lines.

3D NAND broadly consists of two parts. One is the array that stores data. The other is the peripheral CMOS circuitry responsible for read/write operations and control. The traditional approach fabricates both parts on the same wafer, but they have different temperaments. The memory array requires a high number of layers and high-temperature processing, while the peripheral circuitry prefers logic processes better suited to high speed and low power. When the two are bound together, both design and manufacturing must compromise with each other.

YMTC’s Xtacking separates them.

The memory array is fabricated on one wafer, and the peripheral CMOS on another. Each side gets to choose an appropriate process. Afterward, the two are combined into a single chip through wafer-level hybrid bonding and massive metal interconnects. Peripheral circuits no longer occupy area beside the array, and logic and memory can be developed in parallel. YMTC claims this approach can shorten product development time by at least three months and cut manufacturing cycle time by roughly 20%. This is the company’s stated figure, but the engineering value behind it is easy to understand: two teams no longer have to squeeze onto the same process line waiting for each other.

Even more critical is the timeline. Xtacking was officially unveiled in 2018, and the second-generation 3D NAND using this architecture entered mass production in 2019. It then continued to evolve through 3.0 and 4.0. According to YMTC’s official timeline, the fifth-generation TLC product entered mass production in 2024, and the fifth-generation QLC product entered mass production in 2025.

Of course, separately manufacturing the array and CMOS was not an isolated concept invented from scratch by YMTC. Toshiba Memory — the entity that later became Kioxia — had related bonding patent priority dating back to 2014. Kioxia later branded its own technology CBA and used it for BiCS8 mass production.

This actually makes Xtacking’s value clearer: Kioxia had earlier foundational patents, while YMTC achieved earlier volume production. According to public timelines, from YMTC’s 2019 mass production of Xtacking products to Kioxia’s 2024 mass production of BiCS8 using CBA, the gap is roughly five years.

The semiconductor industry ultimately does not score points based on who first voiced a concept, but on who can turn a concept into a product, push the product to acceptable yields, and convert those yields into cost advantages. Filing patents early is one kind of capability; ironing out tens of thousands of process steps to sustain continuous production is another, far harder capability to replicate.

The most important thing about Xtacking is not that it gave China’s memory industry a catchy new name, but that it completed a full closed loop from architecture to patents to mass production. That is not common in China’s semiconductor history.

Patents Are Not a Wall, More Like an Interleaved Minefield

Whenever 4F² or Xtacking comes up, someone will inevitably ask: who actually owns this technology? If others adopt a similar structure, must they pay royalties?

Reality is not that clean-cut.

4F² is first and foremost a cell area metric, not a blanket license that any single company can exclusively own. Related cell layout patents appeared as early as the last century, and some of those early patents have now expired. The patents that still matter are scattered across vertical channel transistors, buried bit lines, self-aligned contacts, oxide materials, capacitor structures, bonding interfaces, and control methods. Samsung, SK Hynix, Intel, Applied Materials, CXMT, and Kioxia all have their own portfolios.

Hybrid bonding follows the same logic. YMTC holds a combination of patents around the specific implementation of Xtacking, while Kioxia, Samsung, Intel, and others also hold their own bonding and array integration patents. The mere fact that two products both separate the array from peripheral circuits does not directly prove copying, let alone imply that all later entrants must pay a particular company.

But this does not mean YMTC’s patents are merely decorative. It has already sued Micron in the United States over 3D NAND technology. Court documents from January 2026 show that among the 19 patents involved in the case, the PTAB instituted inter partes review for 14 and declined for the other 5. The disputes over infringement and patent validity had not yet reached a final ruling at that time.

This lawsuit does not prove YMTC has already won, but it at least demonstrates that its patent portfolio has real combat value. A patent library that only proves certificate counts domestically is clearly not the same as one that can enter a U.S. court and force a global competitor to respond item by item.

Moreover, the deepest barriers in the memory industry are often not fully written into patents at all. How flat the wafer surface must be polished, how warpage is controlled, how alignment is achieved during bonding, which step is most prone to particle introduction, what equipment parameters widen the yield window — these things live in equipment recipes, failure records, and production line data. Patents tell you where the door is, but they do not hand you the feel of turning the handle.

China, Japan, and Korea Are No Longer Competing on the Same Axis

Simply ranking China, Japan, and Korea in the memory industry today no longer makes much sense.

Korea’s strength lies in today’s high-end commercialization. Samsung has already mass-produced and shipped HBM4 built on 1c DRAM and a 4nm logic base die, with peak bandwidth of up to 3.3TB/s per stack. SK Hynix also holds a clear advantage in HBM customer collaboration, advanced packaging, and AI memory product portfolios. These capabilities ultimately convert into revenue, profit, and the next round of R&D budgets — a gap Chinese manufacturers cannot close with a few papers in the short term.

Japan’s advantage is more like a network buried at the bottom of the industry. Kioxia still has deep accumulation in NAND, bonding, and emerging memory research, and Japanese materials and equipment companies control many critical links. Japan today lacks a large general-purpose DRAM manufacturer that can directly confront Samsung and SK Hynix, but it has never left the global memory technology system.

China presents a rather distinctive state. CXMT is filling out its product portfolio in DDR5, LPDDR5X, and high-end DRAM, while YMTC continues advancing its 3D NAND generations. At the same time, Xtacking and 4F² vertical channel transistors have given China its own technological labels.

This is not “stronger than Japan and Korea in every category.” Rather, China can no longer only chase along routes that Japan and Korea have already drawn. Current products, next-generation devices, and new architecture mass production are now advancing on three fronts simultaneously.

I think this is the most significant change in China’s memory industry worth paying attention to.

What Chinese manufacturing is truly good at has never been just making a mature product cheaper. It is better at decomposing complex problems into a large number of measurable, adjustable steps, and then iterating repeatedly across equipment, materials, processes, and production line data. Wafer separation, hybrid bonding, and vertical transistors are precisely the kind of technologies that demand this long, granular systems-engineering capability.

China’s vast markets in smartphones, PCs, automobiles, servers, and data centers can also provide plenty of application feedback. After a memory chip leaves the lab, it must still pass controller adaptation, firmware optimization, system-level certification, and long-term reliability verification. The larger the domestic market, the shorter the feedback loop between product and customer, and the easier it is for failure data to become experience for the next-generation product.

External restrictions have certainly made it harder to acquire equipment, materials, and customers, but they have also forced Chinese companies to look for different solutions earlier. When the mature route becomes increasingly difficult, the relative value of architectural innovation rises. Xtacking did not make advanced lithography unimportant, but by decoupling the array from logic, it redistributed the pressure faced by different processes.

No Need to Rush to Declare Victory, But Stop Pretending Nothing Has Happened

China’s memory industry still has many hard battles to fight. HBM is not simply stacking several DRAM dies; it also involves TSV, logic base dies, advanced packaging, thermal management, and deep collaboration with GPU customers. 4F² must also move beyond 8Gb silicon verification through retention time, power consumption, reliability, cost, and high-volume yield. The self-sufficiency of critical equipment and materials also determines whether technology can be steadily converted into production capacity.

So, “China’s memory industry has comprehensively surpassed Japan and South Korea” is a statement made too early.

But “China’s memory industry is still simply generations behind” has also long stopped being true.

A description closer to reality today is this: Korea still holds the commercial high ground in high-end DRAM and HBM; Japan has deep foundations in NAND, materials, equipment, and foundational patents; and China has already led once in the commercialization of a wafer-separated NAND architecture, and has also taken the early advantage in publicly disclosed full-array silicon verification of next-generation 4F² DRAM.

This lead has boundaries, but it is real. It is not established by layer-count naming or slogans at launch events, but built from silicon wafers, mass production timelines, patent battles, and generations of products.

In the past, China’s memory industry was always answering questions posed by others: whether it could make equivalent DRAM, whether it could catch up to the same NAND layer counts. Now, it is beginning to give its own answers: fabricate the array and CMOS separately, stand planar transistors upright, and use architectural changes to bypass the bottlenecks of the old route.

The next-generation memory card game is far from over. But at least this time, China is no longer waiting outside the door for the outcome.