vlsi

This paper introduces PlaceReasoner-Beta, a verifier-guided multi-agent framework that reformulates macro placement as a reasoning problem for VLSI physical design, achieving significant improvements in timing and wirelength. It also presents PlaceReasoner-Bench, an open benchmark for evaluating methods using routed PPA and DRC.

Chip designer argues AI won't replace chip designers soon, highlighting complex challenges in AI silicon design, and teases a masterclass post covering DAC conference insights and RTL coding.

MAGE is a multimodal multi-agent framework that improves macro placement in VLSI physical design by combining structured floorplanning rules, visual checks, and iterative refinement, outperforming commercial placers and human experts on timing metrics.

The paper introduces FusionCell, a dual-modality predictor that fuses layout geometry and netlist topology using a cross-attentive mechanism for accurate and rapid standard-cell performance prediction, achieving 0.92% MAPE and orders of magnitude speedup over traditional simulation.

Proposes MacroDiff+, a physics-guided geometric diffusion framework for macro placement in VLSI design, achieving 6.1–6.2% wirelength reduction on ISPD2005 benchmarks with superior stability and scalability.

Historical 1990 paper from Amdahl detailing the design of a 20 MIPS mainframe processor built with 20,000 logic gates.